miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: x400: Upgrade to Vivado 2021.1

Browse Source 
Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 6193c765fe
commit 1b952d33df
27 changed files with 1156 additions and 692 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl
+26 -40
View File
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
@@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } {
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } {
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -167,14 +167,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
@@ -189,7 +189,6 @@ proc create_root_design { parentCell } {
set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -203,7 +202,6 @@ proc create_root_design { parentCell } {
set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -217,7 +215,6 @@ proc create_root_design { parentCell } {
set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -231,7 +228,6 @@ proc create_root_design { parentCell } {
set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -245,7 +241,6 @@ proc create_root_design { parentCell } {
set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -262,7 +257,6 @@ proc create_root_design { parentCell } {
set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -276,7 +270,6 @@ proc create_root_design { parentCell } {
set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -290,7 +283,6 @@ proc create_root_design { parentCell } {
set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -304,7 +296,6 @@ proc create_root_design { parentCell } {
set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -321,7 +312,6 @@ proc create_root_design { parentCell } {
set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -335,7 +325,6 @@ proc create_root_design { parentCell } {
set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -349,7 +338,6 @@ proc create_root_design { parentCell } {
set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
@@ -366,7 +354,6 @@ proc create_root_design { parentCell } {
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
@@ -395,12 +382,11 @@ proc create_root_design { parentCell } {
# Create ports
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
@@ -430,18 +416,18 @@ proc create_root_design { parentCell } {
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
# Create address segments
create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg
assign_bd_address -offset 0x00000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] -force
assign_bd_address -offset 0x00010000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] -force
assign_bd_address -offset 0x00020000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] -force
assign_bd_address -offset 0x00030000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] -force
assign_bd_address -offset 0x0000C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] -force
assign_bd_address -offset 0x0001C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] -force
assign_bd_address -offset 0x0002C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] -force
assign_bd_address -offset 0x0003C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] -force
assign_bd_address -offset 0x00008000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] -force
assign_bd_address -offset 0x00018000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] -force
assign_bd_address -offset 0x00028000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] -force
assign_bd_address -offset 0x00038000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] -force
# Restore current instance