fpga: x400: Upgrade to Vivado 2021.1
Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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@@ -100,11 +100,11 @@ if { ${design_name} eq "" } {
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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@@ -113,10 +113,10 @@ if { ${design_name} eq "" } {
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set_property USER_COMMENTS.comment_0 "Note 1: The ID width of the AXI interconnect (xbar) master changes depending on the axi_interconnect optimization strategy. It will be zero for 'minimize area' and non-zero for 'maximize performance'.
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Note 2: I have explicitly set ID width to 1 on the input ports to match our AXI master and to 4 on the output block to match the DRAM slave." [get_bd_designs $design_name]
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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@@ -133,7 +133,7 @@ xilinx.com:ip:axi_register_slice:2.1\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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@@ -143,14 +143,14 @@ xilinx.com:ip:axi_register_slice:2.1\
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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@@ -174,14 +174,14 @@ proc create_root_design { parentCell } {
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -226,7 +226,6 @@ proc create_root_design { parentCell } {
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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@@ -259,7 +258,6 @@ proc create_root_design { parentCell } {
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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@@ -292,7 +290,6 @@ proc create_root_design { parentCell } {
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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@@ -325,7 +322,6 @@ proc create_root_design { parentCell } {
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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@@ -337,21 +333,19 @@ proc create_root_design { parentCell } {
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# Create ports
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set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ]
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set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
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CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
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CONFIG.FREQ_HZ {350000000} \
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] $M0_AXI_ACLK
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set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_LOW} \
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] $M0_AXI_ARESETN
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set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ]
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set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \
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CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
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CONFIG.FREQ_HZ {350000000} \
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] $S0_AXI_ACLK
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set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
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@@ -360,6 +354,276 @@ proc create_root_design { parentCell } {
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set_property -dict [ list \
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CONFIG.DATA_WIDTH {256} \
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CONFIG.ID_WIDTH {4} \
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CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A00_ADDR_WIDTH {0} \
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CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A00_ADDR_WIDTH {0} \
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CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A00_ADDR_WIDTH {0} \
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CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A00_ADDR_WIDTH {0} \
|
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CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A00_ADDR_WIDTH {0} \
|
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CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {4} \
|
||||
CONFIG.S01_BASE_ID {0x00000004} \
|
||||
@@ -549,10 +813,10 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_4/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_7/aresetn] [get_bd_pins axi_register_slice_8/aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
Reference in New Issue
Block a user