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fpga: x400: Upgrade to Vivado 2021.1

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Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 6193c765fe
commit 1b952d33df
27 changed files with 1156 additions and 692 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/ip/adc_400m_bd/adc_400m_bd.tcl
+29 -34
View File
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
@@ -107,11 +107,11 @@ if { ${design_name} eq "" } {
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
@@ -119,10 +119,10 @@ if { ${design_name} eq "" } {
# Add USER_COMMENTS on $design_name
set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
@@ -139,7 +139,7 @@ xilinx.com:ip:fir_compiler:7.2\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -149,7 +149,7 @@ xilinx.com:ip:fir_compiler:7.2\
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
@@ -168,7 +168,7 @@ scale_2x\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
@@ -177,14 +177,14 @@ scale_2x\
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -208,14 +208,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
@@ -263,22 +263,17 @@ proc create_root_design { parentCell } {
# Create ports
set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ]
set data_clk [ create_bd_port -dir I -type clk data_clk ]
set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {adc_data_out_resetn_dclk} \
CONFIG.FREQ_HZ {122880000} \
] $data_clk
set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ]
set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ]
set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ]
set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {fir_resetn_rclk2x} \
CONFIG.FREQ_HZ {368640000} \
] $rfdc_clk_2x
set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ]
@@ -294,10 +289,10 @@ proc create_root_design { parentCell } {
set block_name adc_gearbox_2x4
set block_cell_name adc_gearbox_2x4_0
if { [catch {set adc_gearbox_2x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_gearbox_2x4_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
@@ -305,10 +300,10 @@ proc create_root_design { parentCell } {
set block_name adc_gearbox_8x4
set block_cell_name adc_gearbox_8x4_0
if { [catch {set adc_gearbox_8x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_gearbox_8x4_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
@@ -333,10 +328,10 @@ proc create_root_design { parentCell } {
set block_name ddc_400m_saturate
set block_cell_name ddc_400m_saturate_0
if { [catch {set ddc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $ddc_400m_saturate_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
@@ -344,13 +339,13 @@ proc create_root_design { parentCell } {
set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ]
set_property -dict [ list \
CONFIG.Clock_Frequency {384} \
CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2} \
CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2}\
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {26} \
CONFIG.ColumnConfig {13} \
CONFIG.Decimation_Rate {3} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
@@ -372,10 +367,10 @@ proc create_root_design { parentCell } {
set block_name scale_2x
set block_cell_name scale_2x_0
if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $scale_2x_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \