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fpga: x400: Add 1x64, 2x64, and 1x128 DRAM interconnect

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Original-commit: daf1ed2ad2fbb72f16a9909fa75a0ba9e2879583
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent dd2b935f4b
commit 0e65ae3c86
8 changed files with 2022 additions and 325 deletions
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top/x400/ip/axi_inter_1x64_512_bd/Makefile.inc
+32
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#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_1X64_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x64_512_bd/, \
axi_inter_1x64_512_bd.tcl \
)
IP_AXI_INTER_1X64_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
axi_inter_1x64_512_bd.tcl \
)
IP_AXI_INTER_1X64_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
axi_inter_1x64_512_bd/axi_inter_1x64_512_bd.bd \
)
BD_AXI_INTER_1X64_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
axi_inter_1x64_512_bd.bd.out \
axi_inter_1x64_512_bd/axi_inter_1x64_512_bd_ooc.xdc \
axi_inter_1x64_512_bd/synth/axi_inter_1x64_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_1X64_512_BD_TRGT
$(IP_AXI_INTER_1X64_512_BD_SRCS) $(BD_AXI_INTER_1X64_512_BD_OUTS) $(IP_AXI_INTER_1X64_512_BDTCL_SRCS): IP_AXI_INTER_1X64_512_BD_TRGT
@:
IP_AXI_INTER_1X64_512_BD_TRGT: $(IP_AXI_INTER_1X64_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_1x64_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)