fpga: e31x: Upgrade to Vivado 2021.1
Original-commit: 77f921c7c5d06095af5eb86a209348251edef07d
This commit is contained in:
Sam O'Brien
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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@@ -43,7 +43,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z020clg484-3
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create_project project_1 myproj -part xc7z020clg484-1
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}
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@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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@@ -128,7 +128,7 @@ xilinx.com:ip:axi_crossbar:2.1\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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@@ -138,14 +138,14 @@ xilinx.com:ip:axi_crossbar:2.1\
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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@@ -169,14 +169,14 @@ proc create_root_design { parentCell } {
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -191,7 +191,6 @@ proc create_root_design { parentCell } {
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set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {29} \
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \
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CONFIG.DATA_WIDTH {128} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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@@ -204,7 +203,6 @@ proc create_root_design { parentCell } {
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \
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CONFIG.DATA_WIDTH {64} \
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CONFIG.FREQ_HZ {200000000} \
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CONFIG.HAS_BRESP {1} \
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@@ -237,7 +235,6 @@ proc create_root_design { parentCell } {
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \
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CONFIG.DATA_WIDTH {64} \
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CONFIG.FREQ_HZ {200000000} \
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CONFIG.HAS_BRESP {1} \
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@@ -273,20 +270,18 @@ proc create_root_design { parentCell } {
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \
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] $M00_AXI_ACLK
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set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ]
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set S00_AXI_ACLK [ create_bd_port -dir I -type clk S00_AXI_ACLK ]
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set S00_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 200000000 S00_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {S00_AXI} \
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CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \
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CONFIG.FREQ_HZ {200000000} \
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] $S00_AXI_ACLK
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set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ]
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set S01_AXI_ACLK [ create_bd_port -dir I -type clk S01_AXI_ACLK ]
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set S01_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 200000000 S01_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {S01_AXI} \
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CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \
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CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \
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CONFIG.FREQ_HZ {200000000} \
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] $S01_AXI_ACLK
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set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ]
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@@ -685,8 +680,8 @@ proc create_root_design { parentCell } {
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connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_width_conv/s_axi_aresetn]
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# Create address segments
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create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
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create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
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assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
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assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
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# Restore current instance
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