From 0bb7d1dd932d0cf528a7d4e2309104dafc8f392b Mon Sep 17 00:00:00 2001 From: Sam O'Brien Date: Mon, 31 Jan 2022 11:29:59 -0600 Subject: [PATCH] fpga: e31x: Upgrade to Vivado 2021.1 Original-commit: 77f921c7c5d06095af5eb86a209348251edef07d --- .../axi_inter_2x64_128_bd.tcl | 41 +++++----- top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl | 81 +++++++++---------- top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci | 35 +++++--- .../ip/fifo_short_2clk/fifo_short_2clk.xci | 35 +++++--- top/e31x/setupenv.sh | 2 +- 5 files changed, 105 insertions(+), 89 deletions(-) diff --git a/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl b/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl index e0eb550..f35b5c0 100644 --- a/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl +++ b/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -43,7 +43,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { set list_projs [get_projects -quiet] if { $list_projs eq "" } { - create_project project_1 myproj -part xc7z020clg484-3 + create_project project_1 myproj -part xc7z020clg484-1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -128,7 +128,7 @@ xilinx.com:ip:axi_crossbar:2.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -138,14 +138,14 @@ xilinx.com:ip:axi_crossbar:2.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -169,14 +169,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -191,7 +191,6 @@ proc create_root_design { parentCell } { set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {29} \ - CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \ CONFIG.DATA_WIDTH {128} \ CONFIG.NUM_READ_OUTSTANDING {2} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ @@ -204,7 +203,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \ CONFIG.DATA_WIDTH {64} \ CONFIG.FREQ_HZ {200000000} \ CONFIG.HAS_BRESP {1} \ @@ -237,7 +235,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \ CONFIG.DATA_WIDTH {64} \ CONFIG.FREQ_HZ {200000000} \ CONFIG.HAS_BRESP {1} \ @@ -273,20 +270,18 @@ proc create_root_design { parentCell } { CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \ ] $M00_AXI_ACLK set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ] - set S00_AXI_ACLK [ create_bd_port -dir I -type clk S00_AXI_ACLK ] + set S00_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 200000000 S00_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \ CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \ - CONFIG.FREQ_HZ {200000000} \ ] $S00_AXI_ACLK set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ] - set S01_AXI_ACLK [ create_bd_port -dir I -type clk S01_AXI_ACLK ] + set S01_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 200000000 S01_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S01_AXI} \ CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \ CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \ - CONFIG.FREQ_HZ {200000000} \ ] $S01_AXI_ACLK set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ] @@ -685,8 +680,8 @@ proc create_root_design { parentCell } { connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_width_conv/s_axi_aresetn] # Create address segments - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] -force # Restore current instance diff --git a/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl index 55ab5fa..eedc169 100644 --- a/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl +++ b/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -132,7 +132,7 @@ xilinx.com:ip:axi_protocol_converter:2.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -142,14 +142,14 @@ xilinx.com:ip:axi_protocol_converter:2.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -164,21 +164,21 @@ proc create_hier_cell_dma { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dma() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -279,14 +279,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -417,24 +417,21 @@ proc create_root_design { parentCell } { set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] - set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_GP0_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ - CONFIG.FREQ_HZ {40000000} \ ] $S_AXI_GP0_ACLK set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] - set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ CONFIG.ASSOCIATED_RESET {bus_rstn} \ - CONFIG.FREQ_HZ {200000000} \ ] $bus_clk set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axi_pmu:m_axi_xbar:m_axi_eth_internal} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] @@ -784,8 +781,12 @@ proc create_root_design { parentCell } { CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_9_PULLUP {enabled} \ CONFIG.PCW_MIO_9_SLEW {slow} \ - CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ - CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET\ +Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet\ +0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART\ +1#UART 1#GPIO#GPIO#Enet 0#Enet 0}\ + CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio}\ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_PJTAG_PJTAG_IO {