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e320: Swap out liberio for internal Ethernet

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Original-commit: d01e091c4c7ccc323d305580a27754918b02974b
This commit is contained in:
Alex Williams
2020-07-16 10:00:12 -05:00
committed by Aaron Rossetto
parent c33435c1b9
commit 08c24691a9
4 changed files with 579 additions and 567 deletions
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top/e320/e320.v
+141 -31
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@@ -297,25 +297,51 @@ module e320 (
wire [1:0] m_axi_eth_dma_bresp;
wire [1:0] m_axi_eth_dma_rresp;
wire [31:0] m_axi_eth_dma_rdata;
wire m_axi_eth_internal_arvalid;
wire m_axi_eth_internal_awvalid;
wire m_axi_eth_internal_bready;
wire m_axi_eth_internal_rready;
wire m_axi_eth_internal_wvalid;
wire [31:0] m_axi_eth_internal_araddr;
wire [31:0] m_axi_eth_internal_awaddr;
wire [31:0] m_axi_eth_internal_wdata;
wire [3:0] m_axi_eth_internal_wstrb;
wire m_axi_eth_internal_arready;
wire m_axi_eth_internal_awready;
wire m_axi_eth_internal_bvalid;
wire m_axi_eth_internal_rvalid;
wire m_axi_eth_internal_wready;
wire [1:0] m_axi_eth_internal_bresp;
wire [1:0] m_axi_eth_internal_rresp;
wire [31:0] m_axi_eth_internal_rdata;
// Processing System
wire [15:0] IRQ_F2P;
// DMA xport adapter to PS
// Internal Ethernet xport adapter to PS
wire [63:0] h2e_tdata;
wire [7:0] h2e_tkeep;
wire h2e_tlast;
wire h2e_tready;
wire h2e_tvalid;
wire [63:0] e2h_tdata;
wire [7:0] e2h_tkeep;
wire e2h_tlast;
wire e2h_tready;
wire e2h_tvalid;
wire [63:0] m_axis_dma_tdata;
wire [3:0] m_axis_dma_tuser;
wire m_axis_dma_tlast;
wire m_axis_dma_tready;
wire m_axis_dma_tvalid;
wire [63:0] s_axis_dma_tdata;
wire [3:0] s_axis_dma_tdest;
wire s_axis_dma_tlast;
wire s_axis_dma_tready;
wire s_axis_dma_tvalid;
// HP0 -- High Performance port 0
wire [5:0] s_axi_hp0_awid;
wire [31:0] s_axi_hp0_awaddr;
wire [2:0] s_axi_hp0_awprot;
wire s_axi_hp0_awvalid;
@@ -327,7 +353,6 @@ module e320 (
wire [1:0] s_axi_hp0_bresp;
wire s_axi_hp0_bvalid;
wire s_axi_hp0_bready;
wire [5:0] s_axi_hp0_arid;
wire [31:0] s_axi_hp0_araddr;
wire [2:0] s_axi_hp0_arprot;
wire s_axi_hp0_arvalid;
@@ -347,7 +372,6 @@ module e320 (
wire [1:0] s_axi_hp0_arburst;
wire [2:0] s_axi_hp0_arsize;
wire [4:0] s_axi_eth_descriptor_awid;
wire [31:0] s_axi_eth_descriptor_awaddr;
wire [2:0] s_axi_eth_descriptor_awprot;
wire s_axi_eth_descriptor_awvalid;
@@ -359,7 +383,6 @@ module e320 (
wire [1:0] s_axi_eth_descriptor_bresp;
wire s_axi_eth_descriptor_bvalid;
wire s_axi_eth_descriptor_bready;
wire [4:0] s_axi_eth_descriptor_arid;
wire [31:0] s_axi_eth_descriptor_araddr;
wire [2:0] s_axi_eth_descriptor_arprot;
wire s_axi_eth_descriptor_arvalid;
@@ -1147,9 +1170,6 @@ module e320 (
assign IRQ_F2P[0] = arm_eth_rx_irq;
assign IRQ_F2P[1] = arm_eth_tx_irq;
assign {s_axi_hp0_awid, s_axi_hp0_arid} = 12'd0;
assign {s_axi_eth_descriptor_awid, s_axi_eth_descriptor_arid} = 10'd0;
axi_eth_dma inst_axi_eth_dma (
.s_axi_lite_aclk(clk40),
.m_axi_sg_aclk(clk40),
@@ -1284,6 +1304,83 @@ module e320 (
.o_tready(arm_eth_rx_tready)
);
/////////////////////////////////////////////////////////////////////
//
// Internal Ethernet Interface
//
//////////////////////////////////////////////////////////////////////
eth_internal #(
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1)
) eth_internal_i (
// Resets
.bus_rst (bus_rst),
// Clocks
.bus_clk (bus_clk),
//Axi-lite
.s_axi_aclk (clk40),
.s_axi_aresetn (clk40_rstn),
.s_axi_awaddr (m_axi_eth_internal_awaddr),
.s_axi_awvalid (m_axi_eth_internal_awvalid),
.s_axi_awready (m_axi_eth_internal_awready),
.s_axi_wdata (m_axi_eth_internal_wdata),
.s_axi_wstrb (m_axi_eth_internal_wstrb),
.s_axi_wvalid (m_axi_eth_internal_wvalid),
.s_axi_wready (m_axi_eth_internal_wready),
.s_axi_bresp (m_axi_eth_internal_bresp),
.s_axi_bvalid (m_axi_eth_internal_bvalid),
.s_axi_bready (m_axi_eth_internal_bready),
.s_axi_araddr (m_axi_eth_internal_araddr),
.s_axi_arvalid (m_axi_eth_internal_arvalid),
.s_axi_arready (m_axi_eth_internal_arready),
.s_axi_rdata (m_axi_eth_internal_rdata),
.s_axi_rresp (m_axi_eth_internal_rresp),
.s_axi_rvalid (m_axi_eth_internal_rvalid),
.s_axi_rready (m_axi_eth_internal_rready),
// Host-Ethernet DMA interface
.e2h_tdata (e2h_tdata),
.e2h_tkeep (e2h_tkeep),
.e2h_tlast (e2h_tlast),
.e2h_tvalid (e2h_tvalid),
.e2h_tready (e2h_tready),
.h2e_tdata (h2e_tdata),
.h2e_tkeep (h2e_tkeep),
.h2e_tlast (h2e_tlast),
.h2e_tvalid (h2e_tvalid),
.h2e_tready (h2e_tready),
// Vita router interface
.e2v_tdata (m_axis_dma_tdata),
.e2v_tlast (m_axis_dma_tlast),
.e2v_tvalid (m_axis_dma_tvalid),
.e2v_tready (m_axis_dma_tready),
.v2e_tdata (s_axis_dma_tdata),
.v2e_tlast (s_axis_dma_tlast),
.v2e_tvalid (s_axis_dma_tvalid),
.v2e_tready (s_axis_dma_tready),
// MISC
.port_info (),
.device_id (device_id),
.link_up (),
.activity ()
);
/////////////////////////////////////////////////////////////////////
//
// PS Connections
@@ -1373,7 +1470,6 @@ module e320 (
.s_axi_eth_descriptor_araddr(s_axi_eth_descriptor_araddr),
.s_axi_eth_descriptor_arburst(s_axi_eth_descriptor_arburst),
.s_axi_eth_descriptor_arcache(s_axi_eth_descriptor_arcache),
.s_axi_eth_descriptor_arid(s_axi_eth_descriptor_arid),
.s_axi_eth_descriptor_arlen(s_axi_eth_descriptor_arlen),
.s_axi_eth_descriptor_arlock(1'b0),
.s_axi_eth_descriptor_arprot(s_axi_eth_descriptor_arprot),
@@ -1384,7 +1480,6 @@ module e320 (
.s_axi_eth_descriptor_awaddr(s_axi_eth_descriptor_awaddr),
.s_axi_eth_descriptor_awburst(s_axi_eth_descriptor_awburst),
.s_axi_eth_descriptor_awcache(s_axi_eth_descriptor_awcache),
.s_axi_eth_descriptor_awid(s_axi_eth_descriptor_awid),
.s_axi_eth_descriptor_awlen(s_axi_eth_descriptor_awlen),
.s_axi_eth_descriptor_awlock(1'b0),
.s_axi_eth_descriptor_awprot(s_axi_eth_descriptor_awprot),
@@ -1392,12 +1487,10 @@ module e320 (
.s_axi_eth_descriptor_awready(s_axi_eth_descriptor_awready),
.s_axi_eth_descriptor_awsize(s_axi_eth_descriptor_awsize),
.s_axi_eth_descriptor_awvalid(s_axi_eth_descriptor_awvalid),
.s_axi_eth_descriptor_bid(),
.s_axi_eth_descriptor_bready(s_axi_eth_descriptor_bready),
.s_axi_eth_descriptor_bresp(s_axi_eth_descriptor_bresp),
.s_axi_eth_descriptor_bvalid(s_axi_eth_descriptor_bvalid),
.s_axi_eth_descriptor_rdata(s_axi_eth_descriptor_rdata),
.s_axi_eth_descriptor_rid(),
.s_axi_eth_descriptor_rlast(s_axi_eth_descriptor_rlast),
.s_axi_eth_descriptor_rready(s_axi_eth_descriptor_rready),
.s_axi_eth_descriptor_rresp(s_axi_eth_descriptor_rresp),
@@ -1414,31 +1507,29 @@ module e320 (
.S_AXI_HP0_araddr(s_axi_hp0_araddr),
.S_AXI_HP0_arburst(s_axi_hp0_arburst),
.S_AXI_HP0_arcache(s_axi_hp0_arcache),
.S_AXI_HP0_arid(s_axi_hp0_arid),
.S_AXI_HP0_arlen(s_axi_hp0_arlen),
.S_AXI_HP0_arlock(1'b0),
.S_AXI_HP0_arprot(s_axi_hp0_arprot),
.S_AXI_HP0_arqos(4'b0),
.S_AXI_HP0_arready(s_axi_hp0_arready),
.S_AXI_HP0_arregion(4'b0),
.S_AXI_HP0_arsize(s_axi_hp0_arsize),
.S_AXI_HP0_arvalid(s_axi_hp0_arvalid),
.S_AXI_HP0_awaddr(s_axi_hp0_awaddr),
.S_AXI_HP0_awburst(s_axi_hp0_awburst),
.S_AXI_HP0_awcache(s_axi_hp0_awcache),
.S_AXI_HP0_awid(s_axi_hp0_awid),
.S_AXI_HP0_awlen(s_axi_hp0_awlen),
.S_AXI_HP0_awlock(1'b0),
.S_AXI_HP0_awprot(s_axi_hp0_awprot),
.S_AXI_HP0_awqos(4'b0),
.S_AXI_HP0_awready(s_axi_hp0_awready),
.S_AXI_HP0_awregion(4'b0),
.S_AXI_HP0_awsize(s_axi_hp0_awsize),
.S_AXI_HP0_awvalid(s_axi_hp0_awvalid),
.S_AXI_HP0_bid(),
.S_AXI_HP0_bready(s_axi_hp0_bready),
.S_AXI_HP0_bresp(s_axi_hp0_bresp),
.S_AXI_HP0_bvalid(s_axi_hp0_bvalid),
.S_AXI_HP0_rdata(s_axi_hp0_rdata),
.S_AXI_HP0_rid(),
.S_AXI_HP0_rlast(s_axi_hp0_rlast),
.S_AXI_HP0_rready(s_axi_hp0_rready),
.S_AXI_HP0_rresp(s_axi_hp0_rresp),
@@ -1448,6 +1539,8 @@ module e320 (
.S_AXI_HP0_wready(s_axi_hp0_wready),
.S_AXI_HP0_wstrb(s_axi_hp0_wstrb),
.S_AXI_HP0_wvalid(s_axi_hp0_wvalid),
// Ethernet DMA engines
.m_axi_eth_dma_araddr(m_axi_eth_dma_araddr),
.m_axi_eth_dma_arprot(),
.m_axi_eth_dma_arready(m_axi_eth_dma_arready),
@@ -1467,6 +1560,25 @@ module e320 (
.m_axi_eth_dma_wready(m_axi_eth_dma_wready),
.m_axi_eth_dma_wstrb(m_axi_eth_dma_wstrb),
.m_axi_eth_dma_wvalid(m_axi_eth_dma_wvalid),
.m_axi_eth_internal_araddr(m_axi_eth_internal_araddr),
.m_axi_eth_internal_arprot(),
.m_axi_eth_internal_arready(m_axi_eth_internal_arready),
.m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid),
.m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr),
.m_axi_eth_internal_awprot(),
.m_axi_eth_internal_awready(m_axi_eth_internal_awready),
.m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid),
.m_axi_eth_internal_bready(m_axi_eth_internal_bready),
.m_axi_eth_internal_bresp(m_axi_eth_internal_bresp),
.m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid),
.m_axi_eth_internal_rdata(m_axi_eth_internal_rdata),
.m_axi_eth_internal_rready(m_axi_eth_internal_rready),
.m_axi_eth_internal_rresp(m_axi_eth_internal_rresp),
.m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid),
.m_axi_eth_internal_wdata(m_axi_eth_internal_wdata),
.m_axi_eth_internal_wready(m_axi_eth_internal_wready),
.m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb),
.m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid),
// MGT IO Regport
.m_axi_net_araddr(m_axi_net_araddr),
@@ -1523,16 +1635,16 @@ module e320 (
.S_AXI_GP0_ARESETN(clk40_rstn),
// DMA
.s_axis_dma_tdata(s_axis_dma_tdata),
.s_axis_dma_tdest(s_axis_dma_tdest),
.s_axis_dma_tlast(s_axis_dma_tlast),
.s_axis_dma_tready(s_axis_dma_tready),
.s_axis_dma_tvalid(s_axis_dma_tvalid),
.m_axis_dma_tdata(m_axis_dma_tdata),
.m_axis_dma_tuser(m_axis_dma_tuser),
.m_axis_dma_tlast(m_axis_dma_tlast),
.m_axis_dma_tready(m_axis_dma_tready),
.m_axis_dma_tvalid(m_axis_dma_tvalid)
.s_axis_dma_tdata(e2h_tdata),
.s_axis_dma_tkeep(e2h_tkeep),
.s_axis_dma_tlast(e2h_tlast),
.s_axis_dma_tready(e2h_tready),
.s_axis_dma_tvalid(e2h_tvalid),
.m_axis_dma_tdata(h2e_tdata),
.m_axis_dma_tkeep(h2e_tkeep),
.m_axis_dma_tlast(h2e_tlast),
.m_axis_dma_tready(h2e_tready),
.m_axis_dma_tvalid(h2e_tvalid)
);
/////////////////////////////////////////////////////////////////////
@@ -1699,15 +1811,13 @@ module e320 (
.rx(rx_flat),
.tx(tx_flat),
// DMA to PS
// Internal Ethernet DMA to PS
.m_dma_tdata(s_axis_dma_tdata),
.m_dma_tdest(s_axis_dma_tdest),
.m_dma_tlast(s_axis_dma_tlast),
.m_dma_tready(s_axis_dma_tready),
.m_dma_tvalid(s_axis_dma_tvalid),
.s_dma_tdata(m_axis_dma_tdata),
.s_dma_tuser(m_axis_dma_tuser),
.s_dma_tlast(m_axis_dma_tlast),
.s_dma_tready(m_axis_dma_tready),
.s_dma_tvalid(m_axis_dma_tvalid),