e320: Swap out liberio for internal Ethernet
Original-commit: d01e091c4c7ccc323d305580a27754918b02974b
This commit is contained in:
Alex Williams
committed by
Aaron Rossetto
Aaron Rossetto
parent
c33435c1b9
commit
08c24691a9
+23
-344
@@ -4,355 +4,34 @@
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*/
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&fpga_full {
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tx_dma0: dma@43CA0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CA0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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tx_dma1: dma@43CB0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CB0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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tx_dma2: dma@43CC0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CC0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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tx_dma3: dma@43CD0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CD0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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tx_dma4: dma@43CE0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CE0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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tx_dma5: dma@43CF0000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43CF0000 0x10000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <0>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <1>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma0: dma@43C00000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C00000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma1: dma@43C10000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C10000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma2: dma@43C20000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C20000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma3: dma@43C30000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C30000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma4: dma@43C40000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C40000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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rx_dma5: dma@43C50000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x43C50000 0x10000>;
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interrupts = <0 52 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 15>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-type = <1>;
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adi,source-bus-width = <0x20>;
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adi,destination-bus-type = <0>;
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adi,destination-bus-width = <0x20>;
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adi,length-width = <24>;
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};
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};
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};
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nixge_internal: ethernet@40020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ni,xge-enet-3.00";
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reg = <0x40020000 0x4000
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0x40030000 0x2000>;
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reg-names = "dma", "ctrl";
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clocks = <&clkc 15>;
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clock-names = "bus_clk";
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usrp_rx_dma0: usrp-rx-dma@43c00000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma0 0>;
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dma-names = "dma";
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port-id = <0>;
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interrupts = <0 52 4>, <0 53 4>;
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interrupt-names = "rx", "tx";
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interrupt-parent = <&intc>;
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status = "okay";
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regmap = <&dma_conf0>;
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offset = <0x0>;
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phy-mode = "internal";
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local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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usrp_rx_dma1: usrp-rx-dma@43c10000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma1 0>;
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dma-names = "dma";
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port-id = <1>;
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regmap = <&dma_conf0>;
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offset = <0x4>;
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};
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usrp_rx_dma2: usrp-rx-dma@43c20000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma2 0>;
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dma-names = "dma";
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port-id = <2>;
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regmap = <&dma_conf0>;
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offset = <0x8>;
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};
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usrp_rx_dma3: usrp-rx-dma@43c30000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma3 0>;
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dma-names = "dma";
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port-id = <3>;
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regmap = <&dma_conf0>;
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offset = <0xc>;
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};
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usrp_rx_dma4: usrp-rx-dma@43c40000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma4 0>;
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dma-names = "dma";
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port-id = <4>;
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regmap = <&dma_conf0>;
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offset = <0x10>;
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};
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usrp_rx_dma5: usrp-rx-dma@43c50000 {
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compatible = "ettus,usrp-rx-dma";
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dmas = <&rx_dma5 0>;
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dma-names = "dma";
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port-id = <5>;
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regmap = <&dma_conf0>;
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offset = <0x14>;
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};
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usrp_tx_dma0: usrp-tx-dma@43ca0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma0 0>;
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dma-names = "dma";
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port-id = <0>;
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};
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usrp_tx_dma1: usrp-tx-dma@43cb0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma1 0>;
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dma-names = "dma";
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port-id = <1>;
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};
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usrp_tx_dma2: usrp-tx-dma@43cc0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma2 0>;
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dma-names = "dma";
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port-id = <2>;
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status = "okay";
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};
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usrp_tx_dma3: usrp-tx-dma@43cd0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma3 0>;
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dma-names = "dma";
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port-id = <3>;
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};
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usrp_tx_dma4: usrp-tx-dma@43ce0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma4 0>;
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dma-names = "dma";
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port-id = <4>;
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status = "okay";
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};
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usrp_tx_dma5: usrp-tx-dma@43cf0000 {
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compatible = "ettus,usrp-tx-dma";
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dmas = <&tx_dma5 0>;
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dma-names = "dma";
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port-id = <5>;
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};
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dma_conf0: dma_conf0@42080000 {
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compatible = "syscon";
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reg = <0x42080000 0x1000>;
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uio@40032000 {
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compatible = "usrp-uio";
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reg = <0x40032000 0x2000>;
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reg-names = "misc-enet-int-regs";
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status = "okay";
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};
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};
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