e31x: Swap out liberio for internal Ethernet
Original-commit: 3f823004600472c7f4b173a0da83a3bd53968c40
This commit is contained in:
RobertWalstab
committed by
Aaron Rossetto
Aaron Rossetto
parent
08c24691a9
commit
0361a8fa3b
+134
-16
@@ -168,6 +168,22 @@ module e31x (
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wire clk40_rstn;
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wire FCLK_RESET0_N;
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//ETH DMA
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wire m_axi_eth_internal_arvalid;
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wire m_axi_eth_internal_awvalid;
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wire m_axi_eth_internal_bready;
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wire m_axi_eth_internal_rready;
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wire m_axi_eth_internal_wvalid;
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wire [31:0] m_axi_eth_internal_araddr;
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wire [31:0] m_axi_eth_internal_awaddr;
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wire [31:0] m_axi_eth_internal_wdata;
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wire [3:0] m_axi_eth_internal_wstrb;
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wire m_axi_eth_internal_rvalid;
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wire m_axi_eth_internal_wready;
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wire [1:0] m_axi_eth_internal_bresp;
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wire [1:0] m_axi_eth_internal_rresp;
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wire [31:0] m_axi_eth_internal_rdata;
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// Crossbar
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wire m_axi_xbar_arvalid;
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wire m_axi_xbar_awvalid;
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@@ -212,15 +228,25 @@ module e31x (
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wire [3:0] m_axi_pmu_wstrb;
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wire m_axi_pmu_wvalid;
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// DMA xport adapter to PS
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// Internal Ethernet xport adapter to PS
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wire [63:0] h2e_tdata;
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wire [7:0] h2e_tkeep;
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wire h2e_tlast;
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wire h2e_tready;
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wire h2e_tvalid;
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wire [63:0] e2h_tdata;
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wire [7:0] e2h_tkeep;
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wire e2h_tlast;
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wire e2h_tready;
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wire e2h_tvalid;
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wire [63:0] m_axis_dma_tdata;
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wire [3:0] m_axis_dma_tuser;
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wire m_axis_dma_tlast;
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wire m_axis_dma_tready;
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wire m_axis_dma_tvalid;
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wire [63:0] s_axis_dma_tdata;
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wire [3:0] s_axis_dma_tdest;
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wire s_axis_dma_tlast;
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wire s_axis_dma_tready;
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wire s_axis_dma_tvalid;
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@@ -354,6 +380,79 @@ module e31x (
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button_press_irq, // Interrupt 30
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1'b0};
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/////////////////////////////////////////////////////////////////////
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//
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// Internal Ethernet Interface
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//
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//////////////////////////////////////////////////////////////////////
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eth_internal #(
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.DWIDTH(REG_DWIDTH),
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.AWIDTH(REG_AWIDTH),
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.PORTNUM(8'd1)
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) eth_internal_i (
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// Resets
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.bus_rst (bus_rst),
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// Clocks
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.bus_clk (bus_clk),
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//Axi-lite
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.s_axi_aclk (clk40),
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.s_axi_aresetn (clk40_rstn),
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.s_axi_awaddr (m_axi_eth_internal_awaddr),
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.s_axi_awvalid (m_axi_eth_internal_awvalid),
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.s_axi_awready (m_axi_eth_internal_awready),
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.s_axi_wdata (m_axi_eth_internal_wdata),
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.s_axi_wstrb (m_axi_eth_internal_wstrb),
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.s_axi_wvalid (m_axi_eth_internal_wvalid),
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.s_axi_wready (m_axi_eth_internal_wready),
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.s_axi_bresp (m_axi_eth_internal_bresp),
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.s_axi_bvalid (m_axi_eth_internal_bvalid),
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.s_axi_bready (m_axi_eth_internal_bready),
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.s_axi_araddr (m_axi_eth_internal_araddr),
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.s_axi_arvalid (m_axi_eth_internal_arvalid),
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.s_axi_arready (m_axi_eth_internal_arready),
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.s_axi_rdata (m_axi_eth_internal_rdata),
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.s_axi_rresp (m_axi_eth_internal_rresp),
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.s_axi_rvalid (m_axi_eth_internal_rvalid),
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.s_axi_rready (m_axi_eth_internal_rready),
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// Host-Ethernet DMA interface
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.e2h_tdata (e2h_tdata),
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.e2h_tkeep (e2h_tkeep),
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.e2h_tlast (e2h_tlast),
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.e2h_tvalid (e2h_tvalid),
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.e2h_tready (e2h_tready),
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.h2e_tdata (h2e_tdata),
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.h2e_tkeep (h2e_tkeep),
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.h2e_tlast (h2e_tlast),
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.h2e_tvalid (h2e_tvalid),
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.h2e_tready (h2e_tready),
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// Vita router interface
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.e2v_tdata (m_axis_dma_tdata),
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.e2v_tlast (m_axis_dma_tlast),
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.e2v_tvalid (m_axis_dma_tvalid),
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.e2v_tready (m_axis_dma_tready),
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.v2e_tdata (s_axis_dma_tdata),
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.v2e_tlast (s_axis_dma_tlast),
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.v2e_tvalid (s_axis_dma_tvalid),
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.v2e_tready (s_axis_dma_tready),
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// MISC
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.port_info (),
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.device_id (device_id),
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.link_up (),
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.activity ()
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);
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/////////////////////////////////////////////////////////////////////
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//
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// PS Connections
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@@ -440,6 +539,27 @@ module e31x (
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.SPI1_SS_O(),
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.SPI1_SS_T(),
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// Ethernet DMA engines
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.m_axi_eth_internal_araddr(m_axi_eth_internal_araddr),
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.m_axi_eth_internal_arprot(),
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.m_axi_eth_internal_arready(m_axi_eth_internal_arready),
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.m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid),
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.m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr),
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.m_axi_eth_internal_awprot(),
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.m_axi_eth_internal_awready(m_axi_eth_internal_awready),
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.m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid),
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.m_axi_eth_internal_bready(m_axi_eth_internal_bready),
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.m_axi_eth_internal_bresp(m_axi_eth_internal_bresp),
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.m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid),
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.m_axi_eth_internal_rdata(m_axi_eth_internal_rdata),
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.m_axi_eth_internal_rready(m_axi_eth_internal_rready),
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.m_axi_eth_internal_rresp(m_axi_eth_internal_rresp),
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.m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid),
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.m_axi_eth_internal_wdata(m_axi_eth_internal_wdata),
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.m_axi_eth_internal_wready(m_axi_eth_internal_wready),
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.m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb),
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.m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid),
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// USB
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.USBIND_0_port_indctl(),
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.USBIND_0_vbus_pwrfault(),
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@@ -495,16 +615,16 @@ module e31x (
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.m_axi_pmu_wvalid(m_axi_pmu_wvalid),
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// DMA
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.s_axis_dma_tdata(s_axis_dma_tdata),
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.s_axis_dma_tdest(s_axis_dma_tdest),
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.s_axis_dma_tlast(s_axis_dma_tlast),
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.s_axis_dma_tready(s_axis_dma_tready),
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.s_axis_dma_tvalid(s_axis_dma_tvalid),
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.m_axis_dma_tdata(m_axis_dma_tdata),
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.m_axis_dma_tuser(m_axis_dma_tuser),
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.m_axis_dma_tlast(m_axis_dma_tlast),
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.m_axis_dma_tready(m_axis_dma_tready),
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.m_axis_dma_tvalid(m_axis_dma_tvalid)
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.s_axis_dma_tdata(e2h_tdata),
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.s_axis_dma_tkeep(e2h_tkeep),
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.s_axis_dma_tlast(e2h_tlast),
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.s_axis_dma_tready(e2h_tready),
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.s_axis_dma_tvalid(e2h_tvalid),
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.m_axis_dma_tdata(h2e_tdata),
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.m_axis_dma_tkeep(h2e_tkeep),
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.m_axis_dma_tlast(h2e_tlast),
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.m_axis_dma_tready(h2e_tready),
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.m_axis_dma_tvalid(h2e_tvalid)
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);
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/////////////////////////////////////////////////////////////////////
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@@ -787,15 +907,13 @@ module e31x (
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.rx(rx_flat),
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.tx(tx_flat),
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// DMA to PS
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// Internal DMA to PS
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.m_dma_tdata(s_axis_dma_tdata),
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.m_dma_tdest(s_axis_dma_tdest),
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.m_dma_tlast(s_axis_dma_tlast),
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.m_dma_tready(s_axis_dma_tready),
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.m_dma_tvalid(s_axis_dma_tvalid),
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.s_dma_tdata(m_axis_dma_tdata),
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.s_dma_tuser(m_axis_dma_tuser),
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.s_dma_tlast(m_axis_dma_tlast),
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.s_dma_tready(m_axis_dma_tready),
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.s_dma_tvalid(m_axis_dma_tvalid),
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