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michael-west d6bcab7c8c FPGA: Add time changed pulse to timekeeper 
The time changed signal was removed and is needed to synchronized the
frontend.  This restores the signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
2023-05-10 14:22:42 -05:00
..
blocks
Replay buffered TX streamer: Fix gaps in TX
2023-04-06 15:34:46 -05:00
core
fpga: rfnoc: Add throttle to stream endpoints
2023-03-13 17:51:17 -04:00
crossbar
fpga: lib: rfnoc: Remove redundant packet gate
2023-02-24 08:07:17 -06:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
fpga: lib: rfnoc: Support multiple port widths on crossbar
2023-02-24 08:07:17 -06:00
utils
FPGA: Add time changed pulse to timekeeper
2023-05-10 14:22:42 -05:00
xport
fpga: lib: Add MTU parameter to eth_internal
2022-09-01 14:41:55 -05:00
xport_sv
fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapter
2023-01-10 14:18:59 -08:00
.gitignore
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
addsub.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
addsub.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_async_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_bit_reduce.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_unsigned.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_deserializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_fir_filter_dec.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter.v
fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
2022-02-10 18:11:41 -07:00
axi_join.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_packer.v
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2020-01-28 09:35:36 -08:00
axi_pipe_join.v
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2020-01-28 09:35:36 -08:00
axi_pipe_mac.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_repeat.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip.v
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2020-01-28 09:35:36 -08:00
axi_round_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_serializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_sync.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
axi_tag_time.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
cadd.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_fifo_large.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_decimate.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_interpolate.v
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2020-01-28 09:35:36 -08:00
cmul.v
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2020-01-28 09:35:36 -08:00
complex_invert.v
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2020-01-28 09:35:36 -08:00
complex_to_mag_approx.v
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2020-01-28 09:35:36 -08:00
complex_to_magsq.v
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2020-01-28 09:35:36 -08:00
conj.v
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2020-01-28 09:35:36 -08:00
const_sreg.v
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2020-01-28 09:35:36 -08:00
const.v
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2020-01-28 09:35:36 -08:00
counter.v
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2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_encoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_modify.v
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2020-01-28 09:35:36 -08:00
cvita_hdr_parser.v
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2020-01-28 09:35:36 -08:00
data_types.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
datapath_gatekeeper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ddc.v
fpga: Update copyright
2023-01-19 15:55:56 -08:00
dds_freq_tune_duc.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
dds_freq_tune.v
FPGA: Fix warnings in dds_freq_tune module
2023-01-19 10:05:27 -06:00
dds_timed.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
dds_wrapper.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
delay_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type2.v
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2020-01-28 09:35:36 -08:00
delay_type3.v
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delay_type4.v
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2020-01-28 09:35:36 -08:00
duc.v
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2020-01-28 09:35:36 -08:00
fft_shift.v
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2020-01-28 09:35:36 -08:00
file_sink.v
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2020-01-28 09:35:36 -08:00
file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
join_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
keep_one_in_n.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh
2022-01-25 14:09:15 -07:00
moving_sum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_add_rc.v
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2020-01-28 09:35:36 -08:00
mult_add.v
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2020-01-28 09:35:36 -08:00
mult_rc.v
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2020-01-28 09:35:36 -08:00
mult.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
multiply.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
noc_traffic_counter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
null_source.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
periodic_framer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
phase_accum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ram_to_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
sine_tone.v
siggen: Fix direction of rotation
2021-10-27 07:56:09 -07:00
split_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00