Wade Fife fd541b0d1a fpga: hls: Add version to generated HLS IP ...

This change causes HLS IP to be exported with a version of 1.0.0
instead of a date code. Due to a bug in Vivado, date codes after
0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting
an explicit revision avoids this issue.

See Xilinx AR 76960 for details.


Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10

2022-01-13 14:33:59 -06:00

..

check_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

git-hash.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ise_jtag_program.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_modelsim.sh

fpga: tools: Detect assertions in ModelSim simulation

2021-06-17 08:16:59 -05:00

launch_vivado.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

launch_vivado.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_vlint.sh

fpga: tools: Put SIM_SRCS at end of compile order

2021-06-17 08:16:59 -05:00

setupenv_base.sh

fpga: tools: Update Vivado scripts to use python3

2021-12-08 12:07:36 -08:00

shared-ip-loc-manage.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_check_syntax.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_gen_ip_makefile.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_gen_part_id.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_generate_bd.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_hls_ip.tcl

fpga: hls: Add version to generated HLS IP

2022-01-13 14:33:59 -06:00

viv_generate_ip.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_patch_ip.tcl

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

viv_hardware_utils.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_ip_utils.tcl

fpga: tools: Ignore BD layout info for TCL-based BD

2020-03-12 10:33:24 -05:00

viv_ip_xci_editor.py

fpga: tools: Add support for RFSoC

2021-06-03 10:22:04 -05:00

viv_sim_project.tcl

fpga: tools: Add UHD_FPGA_DIR definition to synthesis

2021-09-08 08:36:05 -05:00

viv_strategies.tcl

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

viv_synth.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_utils.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

xil_bitfile_parser.py

fpga: Fix Xilinx bitfile parser for Python 3

2021-08-24 09:45:36 -05:00