87 lines
2.4 KiB
Verilog
87 lines
2.4 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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//
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// Removes 6 alignment bytes at the beginning of every packet.
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// This gives us proper alignment to the IP/UDP header.
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//
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// Place an SOF indication in bit[3] of the output tuser.
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//
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module axi64_to_xge64
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(
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input clk,
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input reset,
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input clear,
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input [63:0] s_axis_tdata,
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input [3:0] s_axis_tuser,
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input s_axis_tlast,
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input s_axis_tvalid,
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output s_axis_tready,
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output [63:0] m_axis_tdata,
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output [3:0] m_axis_tuser,
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output m_axis_tlast,
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output m_axis_tvalid,
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input m_axis_tready
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);
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localparam STORE_FIRST = 0;
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localparam FORWARD_FULL = 1;
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localparam RELEASE_LAST = 2;
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reg [1:0] state;
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reg [15:0] saved;
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reg [2:0] last_occ;
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reg last_sof;
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//on last line when eof and not finishing with 7 or 8 bytes as last word.
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wire last_line = (s_axis_tlast && !(s_axis_tuser[2:0] == 3'b111 || s_axis_tuser[2:0] == 3'b000));
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always @(posedge clk) begin
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if(reset | clear) begin
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last_sof <= 0;
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last_occ <= 0;
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state <= STORE_FIRST;
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end
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else begin
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if (s_axis_tvalid && s_axis_tready) begin
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saved <= s_axis_tdata[15:0];
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last_occ <= s_axis_tuser[2:0];
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last_sof <= (state == STORE_FIRST) ;
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end
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case(state)
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STORE_FIRST: begin
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if (s_axis_tvalid && s_axis_tready) begin
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state <= FORWARD_FULL;
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end
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end
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FORWARD_FULL: begin
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if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
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state <= last_line? STORE_FIRST : RELEASE_LAST;
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end
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end
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RELEASE_LAST: begin
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if (m_axis_tvalid && m_axis_tready) begin
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state <= STORE_FIRST;
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end
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end
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endcase //state
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end
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end
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assign m_axis_tdata[63:0] = {saved, s_axis_tdata[63:16]};
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assign m_axis_tuser[3] = last_sof;
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assign m_axis_tlast = (state == RELEASE_LAST)? 1'b1 : last_line;
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assign m_axis_tuser[2:0] = ((state == RELEASE_LAST)? last_occ : (last_line? s_axis_tuser[2:0] : 3'b110)) + 3'b010;
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assign m_axis_tvalid = (state == STORE_FIRST)? 0 : ((state == RELEASE_LAST)? 1 : s_axis_tvalid);
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assign s_axis_tready = (state == STORE_FIRST)? 1 : ((state == RELEASE_LAST)? 0 : m_axis_tready);
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endmodule //fifo69_txrealign
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