30 lines
872 B
Makefile
30 lines
872 B
Makefile
##################################################
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# OpenCore XGE MAC Sources
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##################################################
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XGE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/xge/, \
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rtl/verilog/fault_sm.v \
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rtl/verilog/generic_fifo.v \
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rtl/verilog/generic_fifo_ctrl.v \
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rtl/verilog/generic_mem_xilinx_block.v \
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rtl/verilog/generic_mem_medium.v \
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rtl/verilog/generic_mem_small.v \
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rtl/verilog/meta_sync.v \
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rtl/verilog/meta_sync_single.v \
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rtl/verilog/rx_checker.v \
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rtl/verilog/rx_data_fifo.v \
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rtl/verilog/rx_dequeue.v \
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rtl/verilog/rx_enqueue.v \
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rtl/verilog/rx_hold_fifo.v \
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rtl/verilog/sync_clk_core.v \
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rtl/verilog/sync_clk_wb.v \
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rtl/verilog/sync_clk_xgmii_tx.v \
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rtl/verilog/tx_checker.v \
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rtl/verilog/tx_data_fifo.v \
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rtl/verilog/tx_dequeue.v \
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rtl/verilog/tx_enqueue.v \
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rtl/verilog/tx_hold_fifo.v \
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rtl/verilog/wishbone_if.v \
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rtl/verilog/xge_mac.v \
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))
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