362 lines
9.6 KiB
Verilog
362 lines
9.6 KiB
Verilog
`timescale 1ns/1ps
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module new_tx_tb();
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`ifdef ISIM
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`else //iverilog implied.
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xlnx_glbl glbl (.GSR(),.GTS());
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`endif
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localparam SR_TX_DSP = 8;
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localparam SR_TX_RESPONDER = 16;
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localparam SR_TX_CTRL = 24;
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localparam SR_CYCLES = SR_TX_RESPONDER + 0;
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localparam SR_PACKETS = SR_TX_RESPONDER + 1;
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localparam SR_PHASE_INC = SR_TX_DSP + 0;
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localparam SR_SCALE_FACTOR = SR_TX_DSP + 1;
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localparam SR_INTERP = SR_TX_DSP + 2;
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localparam SR_ERROR_POLICY = SR_TX_CTRL + 0;
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("new_tx_tb.vcd");
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initial $dumpvars(0,new_tx_tb);
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wire run, strobe;
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initial
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begin
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#1000 reset = 0;
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#30000;
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$finish;
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end
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reg [63:0] tdata;
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reg tlast;
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reg tvalid = 1'b0;
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wire tready;
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wire [63:0] i_tdata;
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wire i_tlast, i_tvalid, i_tready;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb = 1'b0;
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reg [63:0] vita_time;
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wire [31:0] sample;
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wire [175:0] sample_tdata;
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wire sample_tready, sample_tvalid;
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wire [11:0] seqnum;
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wire [63:0] error_code;
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wire [31:0] sid;
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reg [31:0] samp0, samp1;
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reg [11:0] seqno;
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wire ack_or_error, packet_consumed;
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//
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// Task Libaray
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//
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task write_setting_bus;
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input [7:0] address;
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input [31:0] data;
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begin
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@(negedge clk);
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set_stb = 1'b0;
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set_addr = 8'h0;
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set_data = 32'h0;
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@(negedge clk);
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set_stb = 1'b1;
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set_addr = address;
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set_data = data;
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@(negedge clk);
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set_stb = 1'b0;
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set_addr = 8'h0;
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set_data = 32'h0;
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end
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endtask // write_setting_bus
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task send_ramp;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] sid;
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reg [31:0] data;
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begin
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seqno = 0;
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data = 0;
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send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
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seqno = seqno + 1;
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data <= data + len;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, data, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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data <= data + len;
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end
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if(burst_count > 1)
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send_packet(len, data, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_ramp
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task send_dc;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] sid;
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reg [31:0] data;
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begin
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seqno = 0;
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data = 1 << 14;
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send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
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seqno = seqno + 1;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, data, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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end
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if(burst_count > 1)
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send_packet(len, data, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_ramp
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task send_burst;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] start_seqnum;
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input send_at;
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input [31:0] sid;
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begin
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seqno = start_seqnum;
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send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
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seqno = seqno + 1;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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end
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if(burst_count > 1)
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_burst
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task send_burst_with_seqid_error;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] start_seqnum;
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input send_at;
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input [31:0] sid;
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begin
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seqno = start_seqnum;
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send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
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seqno = seqno + 1;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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// Add a SeqID error in the middle of the packet burst
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if (seqno == (start_seqnum + burst_count/2))
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seqno = seqno + 1;
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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end
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if(burst_count > 1)
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_burst
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task send_packet;
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input [31:0] len;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] pkt_seqnum;
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input eob;
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input send_at;
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input [31:0] sid;
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begin
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// Send a packet
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samp0 <= start_data;
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samp1 <= start_data + 1;
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@(posedge clk);
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tlast <= 0;
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tdata <= { 1'b0, 1'b0 /*trl*/, send_at, eob, pkt_seqnum, len[15:0]+16'd2+send_at+send_at, sid };
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tvalid <= 1;
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@(posedge clk)
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if(send_at)
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begin
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tdata <= send_time;
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@(posedge clk);
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end
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repeat (len[31:1]+len[0]-1)
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begin
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tdata <= {samp0,samp1};
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samp0 <= samp0 + 2;
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samp1 <= samp1 + 2;
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@(posedge clk);
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end
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tdata <= {samp0,samp1};
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tlast <= 1'b1;
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@(posedge clk);
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tvalid <= 0;
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@(posedge clk);
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end
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endtask // send_packet
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`ifdef SIM_SCRIPT
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// Load simulation script from local directory
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`include "simulation_script.v"
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`else
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initial
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begin
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tvalid <= 1'b0;
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while(reset)
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@(posedge clk);
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write_setting_bus(SR_ERROR_POLICY,32'h4);
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write_setting_bus(SR_PACKETS,32'h8000_0002);
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write_setting_bus(SR_INTERP,32'h1);
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send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
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//send_burst(3/*count*/,6/*len*/,32'hB000_0000/*start*/,64'h0/*time*/,12'h004/*seqnum*/,0/*sendat*/, 32'hDEADBEEF/*sid*/);
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//Intra burst seq_id error
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send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
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// Inter burst sequence error
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send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
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// Single Packet burst, timed
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//send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
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// 2 packet burst, timed
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//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
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//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
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// single odd packet
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//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
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// 2 packet burst, timed, odd
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//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
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//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
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// 2 packet burst, untimed, no eob set
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//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
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//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
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// single packet late
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//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
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end
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`endif // !`ifdef SIM_SCRIPT
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always @(posedge clk)
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if(reset)
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vita_time <= 0;
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else
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vita_time <= vita_time + 1;
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axi_fifo #(.WIDTH(65)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
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.o_tdata({i_tlast,i_tdata}), .o_tvalid(i_tvalid), .o_tready(i_tready));
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new_tx_deframer new_tx_deframer
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready));
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new_tx_control #(.BASE(SR_TX_CTRL)) new_tx_control
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(.clk(clk), .reset(reset), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
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.sample(sample), .run(run), .strobe(strobe),
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.debug()
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);
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wire [63:0] o_tdata;
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wire o_tlast, o_tvalid, o_tready;
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assign o_tready = 1;
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tx_responder #(.BASE(SR_TX_RESPONDER)) tx_responder
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(.clk(clk), .reset(reset), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.vita_time(vita_time),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
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always @(posedge clk)
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if(o_tvalid & o_tready)
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$display("\t\t\t\t\tRESP %x\t%x",o_tdata,o_tlast);
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always @(posedge clk)
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if(~reset)
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begin
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if(strobe & run)
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$display("%x\t%x", vita_time, sample);
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if(strobe & ~run) $display("Spurious Strobe at time %x",vita_time);
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if(packet_consumed) $display("CONSUMED %x", seqnum);
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if(ack_or_error)
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if(error_code[63:32] == 1)
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$display("ACK -- SEQNUM %x", error_code[31:0]);
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else
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$display("ERROR -- SEQNUM %x ERRCODE %x", error_code[31:0],error_code[63:32]);
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end
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wire [23:0] tx_fe_i, tx_fe_q;
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duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
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(.clk(clk), .rst(reset), .clr(1'b0),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
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.sample(sample), .run(run), .strobe(strobe),
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.debug() );
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endmodule // new_tx_tb
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