80 lines
1.4 KiB
Verilog
80 lines
1.4 KiB
Verilog
module float_to_iq
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#(parameter BITS_IN = 32,
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parameter BITS_OUT = 16
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)
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(
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input [31:0] in,
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output [15:0] out
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);
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//flags
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wire neg_inf;
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wire pos_inf;
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wire denorm;
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wire tiny_exp;
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assign pos_inf = (in[31] == 0 && in[30:23] == 1 && in[22:0] == 0);
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assign neg_inf = (in[31] == 1 && in[30:23] == 1 && in[22:0] == 0);
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assign denorm = (in[30:23] == 0);
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assign tiny_exp = (in[30:23] < 'd111);
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wire [23:0] implied_bit_fraction;
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wire [24:0] operation_round;
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wire [15:0] round_fraction;
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wire [15:0] shifted_fraction;
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wire [7:0] shift_val;
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wire [22:0] true_frac;
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assign shift_val = (in[30:23] > 127)? (in[30:23] - 127): (127 - in[30:23]);
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assign implied_bit_fraction = {1'b1,in[22:0]};
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assign operation_round = (implied_bit_fraction + 'h000080);
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//testing for overflow
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assign round_fraction = (operation_round[24] == 0)?(operation_round[23:8]):(16'h7FFF);
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//shift the rounded value
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wire [15:0] shift = round_fraction >> (15 - shift_val);
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//2's complement the shifted output if the signed bit is 1
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wire [15:0] final_val = (in[31] == 1)?(~shift + 1'b1):shift;
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assign out = (pos_inf)?{1'b0,15'h7FFF}:(neg_inf)?{1'b1,15'h8000}:(denorm || tiny_exp)? 16'b0: final_val;
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endmodule
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