263 lines
9.4 KiB
Verilog
263 lines
9.4 KiB
Verilog
//
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// Copyright 2011-2013 Ettus Research LLC
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//
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//! X300/X310 digital down-conversion chain
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module ddc_chain_x300
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#(
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parameter BASE = 0,
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parameter DSPNO = 0,
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parameter WIDTH = 24
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)
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(input clk, input rst, input clr,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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// From RX frontend
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input [WIDTH-1:0] rx_fe_i,
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input [WIDTH-1:0] rx_fe_q,
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// To RX control
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output [31:0] sample,
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input run,
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output strobe,
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output [31:0] debug
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);
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localparam cwidth = 25;
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localparam zwidth = 24;
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wire [31:0] phase_inc;
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reg [31:0] phase;
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wire [17:0] scale_factor;
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wire [cwidth-1:0] i_cordic, q_cordic;
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wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip;
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wire [WIDTH-1:0] i_cic, q_cic;
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wire [46:0] i_hb1, q_hb1;
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wire [46:0] i_hb2, q_hb2;
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wire [47:0] i_hb3, q_hb3;
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wire strobe_cic, strobe_hb1, strobe_hb2, strobe_hb3;
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wire [7:0] cic_decim_rate;
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reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux;
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wire realmode;
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wire swap_iq;
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wire [1:0] hb_rate;
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wire [2:0] enable_hb = { hb_rate == 2'b11, hb_rate[1] == 1'b1, hb_rate != 2'b00 };
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wire reload_go, reload_we1, reload_we2, reload_we3, reload_ld1, reload_ld2, reload_ld3;
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wire [17:0] coef_din;
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setting_reg #(.my_addr(BASE+0)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_inc),.changed());
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setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(scale_factor),.changed());
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setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({hb_rate, cic_decim_rate}),.changed());
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setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({realmode,swap_iq}),.changed());
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setting_reg #(.my_addr(BASE+4), .width(24)) sr_4
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({reload_ld3,reload_we3,reload_ld2,reload_we2,reload_ld1,reload_we1,coef_din}),.changed(reload_go));
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// MUX so we can do realmode signals on either input
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always @(posedge clk)
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if(swap_iq)
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begin
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rx_fe_i_mux <= rx_fe_q;
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rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
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end
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else
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begin
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rx_fe_i_mux <= rx_fe_i;
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rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
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end
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// NCO
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always @(posedge clk)
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if(rst)
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phase <= 0;
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else if(~run)
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phase <= 0;
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else
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phase <= phase + phase_inc;
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//sign extension of cordic input
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wire [cwidth-1:0] to_cordic_i, to_cordic_q;
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
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// CORDIC 24-bit I/O
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cordic_z24 #(.bitwidth(cwidth))
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cordic(.clock(clk), .reset(rst), .enable(run),
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.xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
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.xo(i_cordic),.yo(q_cordic),.zo() );
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clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_cordic_i
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(.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip));
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clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_cordic_q
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(.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));
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// CIC decimator 24 bit I/O
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cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
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.strobe_fast(1'b1),.strobe_slow(strobe_cic) );
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cic_decim #(.bw(WIDTH))
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decim_i (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(i_cordic_clip),.signal_out(i_cic));
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cic_decim #(.bw(WIDTH))
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decim_q (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(q_cordic_clip),.signal_out(q_cic));
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// Halfbands
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wire nd1, nd2, nd3;
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wire rfd1, rfd2, rfd3;
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wire rdy1, rdy2, rdy3;
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wire data_valid1, data_valid2, data_valid3;
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localparam HB1_SCALE = 18;
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localparam HB2_SCALE = 18;
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localparam HB3_SCALE = 18;
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assign strobe_hb1 = data_valid1;
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assign strobe_hb2 = data_valid2;
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assign strobe_hb3 = data_valid3;
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assign nd1 = strobe_cic;
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assign nd2 = strobe_hb1;
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assign nd3 = strobe_hb2;
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hbdec1 hbdec1
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(.clk(clk), // input clk
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.sclr(rst), // input sclr
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.ce(enable_hb[0]), // input ce
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.coef_ld(reload_go & reload_ld1), // input coef_ld
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.coef_we(reload_go & reload_we1), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd1), // output rfd
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.nd(nd1), // input nd
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.din_1(i_cic), // input [23 : 0] din_1
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.din_2(q_cic), // input [23 : 0] din_2
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.rdy(rdy1), // output rdy
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.data_valid(data_valid1), // output data_valid
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.dout_1(i_hb1), // output [46 : 0] dout_1
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.dout_2(q_hb1)); // output [46 : 0] dout_2
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hbdec2 hbdec2
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(.clk(clk), // input clk
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.sclr(rst), // input sclr
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.ce(enable_hb[1]), // input ce
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.coef_ld(reload_go & reload_ld2), // input coef_ld
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.coef_we(reload_go & reload_we2), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd2), // output rfd
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.nd(nd2), // input nd
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.din_1(i_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_1
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.din_2(q_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_2
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.rdy(rdy2), // output rdy
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.data_valid(data_valid2), // output data_valid
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.dout_1(i_hb2), // output [46 : 0] dout_1
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.dout_2(q_hb2)); // output [46 : 0] dout_2
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hbdec3 hbdec3
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(.clk(clk), // input clk
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.sclr(rst), // input sclr
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.ce(enable_hb[2]), // input ce
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.coef_ld(reload_go & reload_ld3), // input coef_ld
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.coef_we(reload_go & reload_we3), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd3), // output rfd
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.nd(strobe_hb2), // input nd
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.din_1(i_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_1
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.din_2(q_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_2
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.rdy(rdy3), // output rdy
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.data_valid(data_valid3), // output data_valid
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.dout_1(i_hb3), // output [47 : 0] dout_1
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.dout_2(q_hb3)); // output [47 : 0] dout_2
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reg [23:0] i_unscaled, q_unscaled;
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reg strobe_unscaled;
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always @(posedge clk)
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case(hb_rate)
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2'd0 :
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begin
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strobe_unscaled <= strobe_cic;
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i_unscaled <= i_cic[23:0];
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q_unscaled <= q_cic[23:0];
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end
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2'd1 :
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begin
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strobe_unscaled <= strobe_hb1;
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i_unscaled <= i_hb1[23+HB1_SCALE:HB1_SCALE];
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q_unscaled <= q_hb1[23+HB1_SCALE:HB1_SCALE];
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end
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2'd2 :
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begin
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strobe_unscaled <= strobe_hb2;
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i_unscaled <= i_hb2[23+HB2_SCALE:HB2_SCALE];
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q_unscaled <= q_hb2[23+HB2_SCALE:HB2_SCALE];
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end
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2'd3 :
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begin
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strobe_unscaled <= strobe_hb3;
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i_unscaled <= i_hb3[23+HB3_SCALE:HB3_SCALE];
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q_unscaled <= q_hb3[23+HB3_SCALE:HB3_SCALE];
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end
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endcase // case (hb_rate)
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wire [42:0] i_scaled, q_scaled;
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wire [23:0] i_clip, q_clip;
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reg strobe_scaled;
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wire strobe_clip;
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MULT_MACRO #(.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(25), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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SCALE_I (.P(i_scaled), // Multiplier output bus, width determined by WIDTH_P parameter
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.A({i_unscaled[23],i_unscaled}), // Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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MULT_MACRO #(.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(25), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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SCALE_Q (.P(q_scaled), // Multiplier output bus, width determined by WIDTH_P parameter
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.A({q_unscaled[23],q_unscaled}), // Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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always @(posedge clk) strobe_scaled <= strobe_unscaled;
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clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_i
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(.clk(clk), .in(i_scaled[42:14]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
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clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_q
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(.clk(clk), .in(q_scaled[42:14]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
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round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16)) round_i
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(.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
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round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16)) round_q
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(.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
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endmodule // ddc_chain
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