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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
157 lines
9.3 KiB
Tcl
157 lines
9.3 KiB
Tcl
#
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# Copyright 2017 Ettus Research, A National Instruments Company
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# SPDX-License-Identifier: LGPL-3.0
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#
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# Daughterboard Pin Definitions for the N310.
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#
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## TDC : ################################################################################
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## Bank 11, 2.5V (DB B)
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#########################################################################################
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set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}]
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set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}]
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set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}]
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set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}]
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set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}]
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set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}]
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### USRP IO B : #########################################################################
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## Bank 11/33
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#########################################################################################
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## HP GPIO, Bank 33, 1.8V
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set_property PACKAGE_PIN J4 [get_ports {DBB_CPLD_PS_SPI_LE}]
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set_property PACKAGE_PIN J3 [get_ports {DBB_CPLD_PS_SPI_SCLK}]
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set_property PACKAGE_PIN D4 [get_ports {DBB_CH1_TX_DSA_DATA[5]}]
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# set_property PACKAGE_PIN D3 [get_ports {nc}]
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set_property PACKAGE_PIN K2 [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}]
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set_property PACKAGE_PIN K3 [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}]
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set_property PACKAGE_PIN B5 [get_ports {DBB_CH1_TX_DSA_DATA[3]}]
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set_property PACKAGE_PIN B4 [get_ports {DBB_CH1_TX_DSA_DATA[4]}]
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set_property PACKAGE_PIN G5 [get_ports {DBB_CPLD_PS_SPI_SDO}]
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set_property PACKAGE_PIN G4 [get_ports {DBB_CPLD_PS_SPI_SDI}]
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set_property PACKAGE_PIN J5 [get_ports {DBB_CH1_RX_DSA_DATA[0]}]
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set_property PACKAGE_PIN K5 [get_ports {DBB_CH1_RX_DSA_DATA[1]}]
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set_property PACKAGE_PIN D5 [get_ports {DBB_CH1_TX_DSA_DATA[2]}]
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set_property PACKAGE_PIN E6 [get_ports {DBB_CH1_TX_DSA_DATA[1]}]
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set_property PACKAGE_PIN L3 [get_ports {DBB_ATR_RX_1}]
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set_property PACKAGE_PIN L2 [get_ports {DBB_ATR_TX_2}]
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set_property PACKAGE_PIN G6 [get_ports {DBB_CH1_TX_DSA_DATA[0]}]
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set_property PACKAGE_PIN H6 [get_ports {DBB_CH1_RX_DSA_DATA[5]}]
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set_property PACKAGE_PIN H4 [get_ports {DBB_ATR_TX_1}]
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set_property PACKAGE_PIN H3 [get_ports {DBB_ATR_RX_2}]
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# set_property PACKAGE_PIN F2 [get_ports {nc}]
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set_property PACKAGE_PIN G2 [get_ports {DBB_CH1_RX_DSA_DATA[3]}]
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set_property PACKAGE_PIN J6 [get_ports {DBB_CH1_RX_DSA_DATA[4]}]
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set_property PACKAGE_PIN K6 [get_ports {DBB_CH1_RX_DSA_DATA[2]}]
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## HR GPIO, Bank 10, 2.5V
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set_property PACKAGE_PIN AK17 [get_ports {DBB_MYK_SYNC_IN_n}]
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set_property PACKAGE_PIN AK18 [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}]
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set_property PACKAGE_PIN AK21 [get_ports {DBB_MYK_SPI_SDO}]
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set_property PACKAGE_PIN AJ21 [get_ports {DBB_MYK_SPI_SDIO}]
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set_property PACKAGE_PIN AF19 [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}]
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set_property PACKAGE_PIN AG19 [get_ports {DBB_CH2_TX_DSA_DATA[5]}]
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set_property PACKAGE_PIN AH19 [get_ports {DBB_CPLD_JTAG_TDI}]
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set_property PACKAGE_PIN AJ19 [get_ports {DBB_CPLD_JTAG_TDO}]
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set_property PACKAGE_PIN AK22 [get_ports {DBB_MYK_GPIO_1}]
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set_property PACKAGE_PIN AK23 [get_ports {DBB_MYK_GPIO_4}]
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set_property PACKAGE_PIN AF20 [get_ports {DBB_CH2_TX_DSA_DATA[4]}]
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set_property PACKAGE_PIN AG20 [get_ports {DBB_CH2_TX_DSA_DATA[3]}]
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set_property PACKAGE_PIN AF23 [get_ports {DBB_MYK_SYNC_OUT_n}]
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set_property PACKAGE_PIN AF24 [get_ports {DBB_CPLD_PL_SPI_SDO}]
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set_property PACKAGE_PIN AK20 [get_ports {DBB_MYK_GPIO_13}]
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set_property PACKAGE_PIN AJ20 [get_ports {DBB_MYK_GPIO_0}]
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set_property PACKAGE_PIN AJ23 [get_ports {DBB_MYK_INTRQ}]
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set_property PACKAGE_PIN AJ24 [get_ports {DBB_CH2_TX_DSA_DATA[2]}]
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set_property PACKAGE_PIN AG24 [get_ports {DBB_CH2_TX_DSA_DATA[0]}]
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set_property PACKAGE_PIN AG25 [get_ports {DBB_CH2_TX_DSA_DATA[1]}]
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set_property PACKAGE_PIN AG21 [get_ports {DBB_FPGA_CLK_P}]
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set_property PACKAGE_PIN AH21 [get_ports {DBB_FPGA_CLK_N}]
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set_property PACKAGE_PIN AE22 [get_ports {DBB_FPGA_SYSREF_P}]
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set_property PACKAGE_PIN AF22 [get_ports {DBB_FPGA_SYSREF_N}]
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set_property PACKAGE_PIN AJ25 [get_ports {DBB_CH2_RX_DSA_DATA[3]}]
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set_property PACKAGE_PIN AK25 [get_ports {DBB_CH2_RX_DSA_DATA[5]}]
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set_property PACKAGE_PIN AB21 [get_ports {DBB_CPLD_JTAG_TMS}]
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set_property PACKAGE_PIN AB22 [get_ports {DBB_CPLD_JTAG_TCK}]
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set_property PACKAGE_PIN AD23 [get_ports {DBB_MYK_GPIO_15}]
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set_property PACKAGE_PIN AE23 [get_ports {DBB_MYK_SPI_CS_n}]
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set_property PACKAGE_PIN AB24 [get_ports {DBB_CH2_RX_DSA_DATA[1]}]
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set_property PACKAGE_PIN AA24 [get_ports {DBB_CH2_RX_DSA_DATA[2]}]
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set_property PACKAGE_PIN AG22 [get_ports {DBB_CPLD_PL_SPI_LE}]
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set_property PACKAGE_PIN AH22 [get_ports {DBB_CPLD_PL_SPI_SDI}]
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set_property PACKAGE_PIN AD21 [get_ports {DBB_MYK_GPIO_12}]
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set_property PACKAGE_PIN AE21 [get_ports {DBB_MYK_GPIO_14}]
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set_property PACKAGE_PIN AC22 [get_ports {DBB_MYK_SPI_SCLK}]
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set_property PACKAGE_PIN AC23 [get_ports {DBB_MYK_GPIO_3}]
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set_property PACKAGE_PIN AC24 [get_ports {DBB_CH2_RX_DSA_DATA[0]}]
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set_property PACKAGE_PIN AD24 [get_ports {DBB_CH2_RX_DSA_DATA[4]}]
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set_property PACKAGE_PIN AH23 [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}]
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set_property PACKAGE_PIN AH24 [get_ports {DBB_CPLD_PL_SPI_SCLK}]
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# set_property PACKAGE_PIN AA25 [get_ports DBB_SWITCHER_CLOCK]
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# set_property IOSTANDARD LVCMOS33 [get_ports DBB_SWITCHER_CLOCK]
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# set_property DRIVE 4 [get_ports DBB_SWITCHER_CLOCK]
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# set_property SLEW SLOW [get_ports DBB_SWITCHER_CLOCK]
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# During SI measurements with default drive strength, many of the FPGA-driven lines to
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# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs
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# we are decreasing the drive strength to the minimum value (4mA) and explicitly
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# declaring the (default) slew rate as SLOW.
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set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \
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DBB_CH1_* \
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DBB_ATR*}]
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set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe
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set_property DRIVE 4 $UsrpIoBHpPinsSe
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set_property SLEW SLOW $UsrpIoBHpPinsSe
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set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \
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DBB_MYK_INTRQ \
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DBB_MYK_SYNC* \
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DBB_MYK_GPIO* \
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DBB_CPLD_PL_* \
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DBB_CPLD_JTAG_* \
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DBB_CH2*}]
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set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSe
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set_property DRIVE 4 $UsrpIoBHrPinsSe
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set_property SLEW SLOW $UsrpIoBHrPinsSe
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set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \
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DBB_FPGA_SYSREF_*}]
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set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff
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set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff
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# Do not allow the DSA lines to float... give them a weak pull if undriven.
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set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}]
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### MGTs, Bank 112
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set_property PACKAGE_PIN W8 [get_ports {USRPIO_B_MGTCLK_P}]
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set_property PACKAGE_PIN W7 [get_ports {USRPIO_B_MGTCLK_N}]
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# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado
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# places the transceivers in the correct places. The mixup in lanes is accounted for
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# in the Mykonos lane crossbar settings.
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set_property PACKAGE_PIN AC4 [get_ports {USRPIO_B_RX_P[0]}]
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set_property PACKAGE_PIN AC3 [get_ports {USRPIO_B_RX_N[0]}]
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set_property PACKAGE_PIN AB6 [get_ports {USRPIO_B_RX_P[1]}]
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set_property PACKAGE_PIN AB5 [get_ports {USRPIO_B_RX_N[1]}]
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set_property PACKAGE_PIN Y6 [get_ports {USRPIO_B_RX_P[2]}]
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set_property PACKAGE_PIN Y5 [get_ports {USRPIO_B_RX_N[2]}]
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set_property PACKAGE_PIN AA4 [get_ports {USRPIO_B_RX_P[3]}]
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set_property PACKAGE_PIN AA3 [get_ports {USRPIO_B_RX_N[3]}]
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set_property PACKAGE_PIN AB2 [get_ports {USRPIO_B_TX_P[0]}]
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set_property PACKAGE_PIN AB1 [get_ports {USRPIO_B_TX_N[0]}]
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set_property PACKAGE_PIN Y2 [get_ports {USRPIO_B_TX_P[1]}]
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set_property PACKAGE_PIN Y1 [get_ports {USRPIO_B_TX_N[1]}]
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set_property PACKAGE_PIN W4 [get_ports {USRPIO_B_TX_P[2]}]
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set_property PACKAGE_PIN W3 [get_ports {USRPIO_B_TX_N[2]}]
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set_property PACKAGE_PIN V2 [get_ports {USRPIO_B_TX_P[3]}]
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set_property PACKAGE_PIN V1 [get_ports {USRPIO_B_TX_N[3]}]
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