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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
 6b67702ad7 Merge FPGA repository back into UHD repository 
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
2020-01-28 09:35:36 -08:00

342 lines
26 KiB
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]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3
-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf
</twCmdLine><twDesign>b200.ncd</twDesign><twDesignPath>b200.ncd</twDesignPath><twPCF>b200.pcf</twPCF><twPcfPath>b200.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx75</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.21 2012-04-23</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twErr" twReportMinPaths="true" dlyHyperLnks="t" ><twItemLimit>10</twItemLimit><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twErrRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="7" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_IFCLK = PERIOD TIMEGRP &quot;IFCLK&quot; 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead><twPinLimitRpt anchorID="8"><twPinLimitBanner>Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP &quot;IFCLK&quot; 10 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_codec_data_clk_p = PERIOD TIMEGRP &quot;codec_data_clk_p&quot; 16.276 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.639</twMinPer></twConstHead><twPinLimitRpt anchorID="10"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP &quot;codec_data_clk_p&quot; 16.276 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5 HIGH 50%;</twConstName><twItemCnt>48903</twItemCnt><twErrCntSetup>2</twErrCntSetup><twErrCntEndPt>2</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>9931</twEndPtCnt><twPathErrCnt>2</twPathErrCnt><twMinPer>12.189</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.189</twSlack><twSrc BELType="FF">slave_fifo32/EP_READY</twSrc><twDest BELType="FF">slave_fifo32/EP_READY1</twDest><twTotPathDel>12.263</twTotPathDel><twClkSkew dest = "1.637" src = "1.328">-0.309</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_READY</twSrc><twDest BELType='FF'>slave_fifo32/EP_READY1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y55.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y55.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_READY</twComp><twBEL>slave_fifo32/EP_READY</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">10.468</twDelInfo><twComp>slave_fifo32/EP_READY</twComp></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_READY1</twComp><twBEL>slave_fifo32/EP_READY1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>10.468</twRouteDel><twTotDel>12.263</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>14.6</twPctLog><twPctRoute>85.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path
</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.341</twSlack><twSrc BELType="FF">slave_fifo32/EP_WMARK</twSrc><twDest BELType="FF">slave_fifo32/EP_WMARK1</twDest><twTotPathDel>11.029</twTotPathDel><twClkSkew dest = "1.642" src = "1.719">0.077</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_WMARK</twSrc><twDest BELType='FF'>slave_fifo32/EP_WMARK1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y78.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y78.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp><twBEL>slave_fifo32/EP_WMARK</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">9.234</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_WMARK1</twComp><twBEL>slave_fifo32/EP_WMARK1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>9.234</twRouteDel><twTotDel>11.029</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>16.3</twPctLog><twPctRoute>83.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="16"><twPinLimitBanner>Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5
HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="17"><twConstRollup name="TS_codec_main_clk" fullName="TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;" type="origin" depth="0" requirement="25.000" prefType="period" actual="16.000" actualRollup="30.473" errors="0" errorRollup="2" items="0" itemsRollup="48903"/><twConstRollup name="TS_gen_clks_clkfx" fullName="TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5 HIGH 50%;" type="child" depth="1" requirement="10.000" prefType="period" actual="12.189" actualRollup="N/A" errors="2" errorRollup="0" items="48903" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="18">1</twUnmetConstCnt><twDataSheet anchorID="19" twNameLen="16"><twClk2SUList anchorID="20" twDestWidth="16"><twDest>codec_main_clk_n</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="21" twDestWidth="16"><twDest>codec_main_clk_p</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twSum anchorID="22"><twErrCnt>2</twErrCnt><twScore>3530</twScore><twSetupScore>3530</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>48903</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12388</twConnCnt></twConstCov><twStats anchorID="23"><twMinPer>16.000</twMinPer><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twTimestamp>Tue Jan 29 17:12:06 2013 </twTimestamp></twFoot><twClientInfo anchorID="24"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 536 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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