b210-k7-fpga/top/b200/coregen/fifo_4k_2clk.veo

/*******************************************************************************
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*                                                                              *
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/*******************************************************************************
*     Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3    *
*                                                                              *
*     Rev 1. The FIFO Generator is a parameterizable first-in/first-out        *
*     memory queue generator. Use it to generate resource and performance      *
*     optimized FIFOs with common or independent read/write clock domains,     *
*     and optional fixed or programmable full and empty flags and              *
*     handshaking signals.  Choose from a selection of memory resource         *
*     types for implementation.  Optional Hamming code based error             *
*     detection and correction as well as error injection capability for       *
*     system test help to insure data integrity.  FIFO width and depth are     *
*     parameterizable, and for native interface FIFOs, asymmetric read and     *
*     write port widths are also supported.                                    *
*******************************************************************************/

// Interfaces:
//    AXI4Stream_MASTER_M_AXIS
//    AXI4Stream_SLAVE_S_AXIS
//    AXI4_MASTER_M_AXI
//    AXI4_SLAVE_S_AXI
//    AXI4Lite_MASTER_M_AXI
//    AXI4Lite_SLAVE_S_AXI
//    master_aclk
//    slave_aclk
//    slave_aresetn

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_4k_2clk your_instance_name (
  .rst(rst), // input rst
  .wr_clk(wr_clk), // input wr_clk
  .rd_clk(rd_clk), // input rd_clk
  .din(din), // input [71 : 0] din
  .wr_en(wr_en), // input wr_en
  .rd_en(rd_en), // input rd_en
  .dout(dout), // output [71 : 0] dout
  .full(full), // output full
  .empty(empty), // output empty
  .rd_data_count(rd_data_count), // output [9 : 0] rd_data_count
  .wr_data_count(wr_data_count) // output [9 : 0] wr_data_count
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file fifo_4k_2clk.v when simulating
// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".