281 lines
8.0 KiB
Systemverilog
281 lines
8.0 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: gearbox_2x1_tb
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//
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// Description: Testbench for gearbox_2x1.
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//
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`default_nettype none
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module gearbox_2x1_tb #(
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parameter IN_WORDS = 2,
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parameter OUT_WORDS = 1,
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parameter BIG_ENDIAN = 0,
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parameter PHASE = 1
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);
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`include "test_exec.svh"
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import PkgTestExec::*;
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localparam WORD_W = 4;
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// Clock periods
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localparam real SLOW_CLK_PER_NS = 10.0;
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localparam real FAST_CLK_PER_NS = SLOW_CLK_PER_NS / 2.0;
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localparam real CLK_IN_PER_NS = (IN_WORDS > OUT_WORDS) ?
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SLOW_CLK_PER_NS : FAST_CLK_PER_NS;
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localparam real CLK_OUT_PER_NS = (OUT_WORDS > IN_WORDS) ?
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SLOW_CLK_PER_NS : FAST_CLK_PER_NS;
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// Give the faster clock a T/2 phase offset
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localparam FAST_CLK_PHASE = PHASE * (FAST_CLK_PER_NS / 2.0);
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localparam real IN_PHASE = (IN_WORDS > OUT_WORDS) ? 0.0 : FAST_CLK_PHASE;
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localparam real OUT_PHASE = (OUT_WORDS > IN_WORDS) ? 0.0 : FAST_CLK_PHASE;
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// Get gearbox total input and output widths
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localparam IN_WORD_W = WORD_W * IN_WORDS;
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localparam OUT_WORD_W = WORD_W * OUT_WORDS;
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// Number of simulation cycles to run for
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localparam NUM_TEST_CYCLES = 50000;
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit i_clk;
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bit o_clk;
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bit i_rst;
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bit o_rst;
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sim_clock_gen #(.PERIOD(CLK_IN_PER_NS), .AUTOSTART(0), .PHASE(IN_PHASE))
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clk_gen_in (.clk(i_clk), .rst(i_rst));
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sim_clock_gen #(.PERIOD(CLK_OUT_PER_NS),.AUTOSTART(0), .PHASE(OUT_PHASE))
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clk_gen_out (.clk(o_clk), .rst(o_rst));
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//---------------------------------------------------------------------------
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// Device Under Test (DUT)
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//---------------------------------------------------------------------------
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bit [ IN_WORD_W-1:0] i_tdata = { IN_WORD_W { 1'bX }};
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bit i_tvalid = 0;
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bit [OUT_WORD_W-1:0] o_tdata;
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bit o_tvalid;
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gearbox_2x1 #(
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.WORD_W (WORD_W),
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.IN_WORDS (IN_WORDS),
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.OUT_WORDS (OUT_WORDS),
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.BIG_ENDIAN (BIG_ENDIAN)
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) gearbox_2x1_i (
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_tdata (i_tdata),
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.i_tvalid (i_tvalid),
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.o_clk (o_clk),
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.o_rst (o_rst),
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.o_tdata (o_tdata),
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.o_tvalid (o_tvalid)
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);
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//---------------------------------------------------------------------------
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// Input Generator
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//---------------------------------------------------------------------------
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bit enable_input = 0;
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longint i_count;
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mailbox #(bit [IN_WORD_W-1:0]) i_queue = new;
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initial forever begin : gen_input
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clk_gen_in.clk_wait_r();
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if (i_rst || !enable_input) begin
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i_tdata <= { IN_WORD_W { 1'bX }};
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i_tvalid <= 1'b0;
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continue;
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end
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// Input randomly to the gearbox
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if ($urandom() % 2 == 0) begin
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bit [ IN_WORD_W-1:0] next_input;
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next_input = $urandom();
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i_count = i_count + 1;
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i_tdata <= next_input;
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i_tvalid <= 1'b1;
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i_queue.put(next_input);
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end else begin
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i_tdata <= { IN_WORD_W { 1'bX }};
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i_tvalid <= 1'b0;
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end
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end : gen_input
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//---------------------------------------------------------------------------
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// Packer/Unpacker
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//---------------------------------------------------------------------------
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//
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// Take the data from i_queue and repack it into o_queue with the correct
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// width and using the correct endianness.
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//
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//---------------------------------------------------------------------------
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mailbox #(bit [OUT_WORD_W-1:0]) o_queue = new;
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initial if (IN_WORDS > OUT_WORDS) begin : unpacker
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bit [IN_WORD_W-1:0] in_word;
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forever begin
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i_queue.get(in_word);
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if (BIG_ENDIAN) begin
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for (int i = IN_WORDS/OUT_WORDS-1; i >= 0; i--) begin
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o_queue.put(in_word[OUT_WORD_W*i +: OUT_WORD_W]);
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end
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end else begin
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for (int i = 0; i < IN_WORDS/OUT_WORDS; i++) begin
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o_queue.put(in_word[OUT_WORD_W*i +: OUT_WORD_W]);
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end
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end
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end
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end else begin : packer
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bit [OUT_WORD_W-1:0] out_word;
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forever begin
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if (BIG_ENDIAN) begin
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for (int i = OUT_WORDS/IN_WORDS-1; i >= 0; i--) begin
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i_queue.get(out_word[IN_WORD_W*i +: IN_WORD_W]);
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end
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end else begin
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for (int i = 0; i < OUT_WORDS/IN_WORDS; i++) begin
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i_queue.get(out_word[IN_WORD_W*i +: IN_WORD_W]);
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end
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end
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o_queue.put(out_word);
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end
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end
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//---------------------------------------------------------------------------
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// Output Checker
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//---------------------------------------------------------------------------
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longint o_count;
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bit [OUT_WORD_W-1:0] expected, actual;
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initial forever begin : check_output
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string msg;
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clk_gen_out.clk_wait_r();
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if (o_rst) begin
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continue;
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end
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if (o_tvalid) begin
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o_count++;
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actual = o_tdata;
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o_queue.get(expected);
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msg = $sformatf("Output didn't match expected value! Expected 0x%0X, received 0x%0X.",
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expected, actual);
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`ASSERT_ERROR(actual == expected, msg);
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end
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end : check_output
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//---------------------------------------------------------------------------
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// Main Test Process
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//---------------------------------------------------------------------------
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initial begin : tb_main
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string msg;
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string tb_name;
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int min_out_words, max_out_words;
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// Initialize the test exec object for this testbench
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tb_name = $sformatf( {
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"gearbox_2x1_tb\n",
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"IN_WORDS = %01d\n",
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"OUT_WORDS = %01d\n",
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"BIG_ENDIAN = %01d\n",
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"PHASE = %01d" },
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IN_WORDS, OUT_WORDS, BIG_ENDIAN, PHASE
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);
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test.start_tb(tb_name);
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// Don't start the clocks until after start_tb() returns. This ensures that
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// the clocks aren't toggling while other instances of this testbench are
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// running, which speeds up simulation time.
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clk_gen_in.start();
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clk_gen_out.start();
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//--------------------------------
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// Reset
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//--------------------------------
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test.start_test("Reset", 10us);
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clk_gen_in.reset();
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clk_gen_out.reset();
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if (i_rst) @i_rst;
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if (o_rst) @o_rst;
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test.end_test();
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//--------------------------------
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// Test Sequences
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//--------------------------------
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test.start_test("Random data", 10ms);
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enable_input <= 1;
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// Let it run for a while
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clk_gen_in.clk_wait_r(NUM_TEST_CYCLES);
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// Stop inputting and wait long enough for any data to propagate through
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enable_input <= 0;
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repeat (8*OUT_WORDS) @i_clk;
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repeat (8*IN_WORDS) @o_clk;
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// Calculate how many words we expect to have received on the output. We
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// might be in the middle of a word, so it might be less than what was
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// input.
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if (OUT_WORDS > IN_WORDS) begin
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min_out_words = ((i_count * IN_WORDS) / OUT_WORDS) * OUT_WORDS;
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max_out_words = min_out_words;
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end else begin
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min_out_words = (i_count-1) * IN_WORDS;
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max_out_words = i_count * IN_WORDS;
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end
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// Make sure the word counts match
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msg = $sformatf("Word counts don't match. Input %0d, output %0d.",
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IN_WORDS*i_count, OUT_WORDS*o_count);
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`ASSERT_ERROR(o_count*OUT_WORDS >= min_out_words &&
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o_count*OUT_WORDS <= max_out_words , msg);
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msg = $sformatf("Only %0d words input. Expected about %0d.",
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i_count*IN_WORDS, 0.5*NUM_TEST_CYCLES*IN_WORDS);
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`ASSERT_ERROR(i_count > 0.4*NUM_TEST_CYCLES, msg);
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$display("Tested %0d output words", o_count);
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test.end_test();
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//--------------------------------
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// Finish Up
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//--------------------------------
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// End the TB, but don't $finish, since we don't want to kill other
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// instances of this testbench that may be running.
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test.end_tb(0);
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// Kill the clocks to end this instance of the testbench
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clk_gen_in.kill();
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clk_gen_out.kill();
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end : tb_main
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endmodule : gearbox_2x1_tb
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`default_nettype wire
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