miegl
90e0b1d038
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim. Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
134 lines
3.8 KiB
Tcl
134 lines
3.8 KiB
Tcl
# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# Exact source manifest for the reconstructed Kintex-7 B210 clone.
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#
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# Paths are repository-relative and are deliberately explicit. Do not replace
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# these lists with recursive globs; doing so can accidentally pull simulation
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# sources into synthesis.
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# Headers active in synthesis
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set B210_GLOBAL_INCLUDE_SOURCES {
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top/b200/Define.vh
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}
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# RTL active in the original sources_1 fileset, in original XPR order
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set B210_HDL_SOURCES {
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lib/dsp/acc.v
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lib/dsp/add2.v
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lib/dsp/add2_and_clip.v
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lib/dsp/add2_and_clip_reg.v
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lib/dsp/add2_and_round.v
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lib/dsp/add2_and_round_reg.v
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lib/dsp/add2_reg.v
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lib/dsp/add_then_mac.v
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lib/fifo/axi_demux4.v
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lib/fifo/axi_fifo.v
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lib/fifo/axi_fifo32_to_fifo64.v
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lib/fifo/axi_fifo64_to_fifo32.v
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lib/fifo/axi_fifo_2clk.v
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lib/fifo/fifo_short_2clk.v
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lib/fifo/fifo_4k_2clk.v
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lib/fifo/fifo_2clk_xpm_core.v
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lib/fifo/axi_fifo_bram.v
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lib/fifo/axi_fifo_flop.v
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lib/fifo/axi_fifo_flop2.v
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lib/fifo_200/axi_fifo_legacy.v
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lib/fifo/axi_fifo_short.v
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lib/fifo/axi_mux4.v
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lib/fifo/axi_packet_gate.v
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top/b200/b200_core.v
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top/b200/b200_io.v
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lib/control/bin2gray.v
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lib/control/binary_encoder.v
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lib/vita_200/chdr_12sc_to_16sc.v
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lib/vita_200/chdr_16sc_to_12sc.v
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lib/vita_200/chdr_16sc_to_32f.v
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lib/vita_200/chdr_16sc_to_8sc.v
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lib/vita_200/chdr_16sc_to_xxxx_chain.v
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lib/vita_200/chdr_32f_to_16sc.v
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lib/vita_200/chdr_8sc_to_16sc.v
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lib/vita_200/chdr_xxxx_to_16sc_chain.v
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lib/dsp/cic_dec_shifter.v
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lib/dsp/cic_decim.v
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lib/dsp/cic_int_shifter.v
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lib/dsp/cic_interp.v
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lib/dsp/cic_strober.v
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lib/dsp/clip.v
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lib/dsp/clip_reg.v
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lib/vita_200/context_packet_gen.v
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lib/dsp/cordic_stage.v
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lib/dsp/cordic_z24.v
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lib/control_200/cvita_uart.v
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lib/dsp/ddc_chain.v
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lib/dsp/duc_chain.v
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top/b200/edge_detect.v
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lib/gpif2/fifo64_to_gpif2.v
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lib/vita_200/float_to_iq.v
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lib/gpif2/gpif2_error_checker.v
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lib/gpif2/gpif2_slave_fifo32.v
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lib/gpif2/gpif2_to_fifo64.v
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lib/control/gpio_atr.v
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lib/control/gpio_atr_io.v
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lib/control/gray2bin.v
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lib/dsp/hb47_int.v
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lib/dsp/hb_dec.v
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lib/dsp/hb_interp.v
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top/b200/coregen_dsp/hbdec1.v
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top/b200/coregen_dsp/hbdec2.v
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lib/vita_200/iq_to_float.v
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lib/vita_200/new_rx_control.v
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lib/vita_200/new_rx_framer.v
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lib/vita_200/new_tx_control.v
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lib/vita_200/new_tx_deframer.v
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lib/timing/pps_generator.v
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top/b200/pps_switch.v
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lib/control_200/radio_ctrl_proc.v
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lib/radio_200/radio_legacy.v
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lib/control/ram_2port.v
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lib/control/reset_sync.v
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lib/dsp/round.v
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lib/dsp/round_reg.v
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lib/dsp/round_sd.v
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lib/control/serial_to_settings.v
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lib/control/setting_reg.v
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lib/dsp/sign_extend.v
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lib/control/simple_spi_core.v
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lib/wishbone/simple_uart.v
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lib/wishbone/simple_uart_rx.v
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lib/wishbone/simple_uart_tx.v
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lib/dsp/small_hb_dec.v
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lib/dsp/small_hb_int.v
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lib/packet_proc_200/source_flow_control_legacy.v
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lib/dsp/srl.v
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lib/control/synchronizer.v
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lib/control/synchronizer_impl.v
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lib/timing/time_compare.v
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lib/timing/timekeeper_legacy.v
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lib/vita_200/trigger_context_pkt.v
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lib/vita_200/tx_responder.v
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lib/control/user_settings.v
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top/b200/b200.v
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}
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# Legacy netlists required by the clone port
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set B210_NETLIST_SOURCES {
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top/b200/coregen_dsp/hbdec2.edif
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top/b200/coregen_dsp/hbdec1.edif
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}
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# Memory initialization files present in the original synthesis fileset
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set B210_MEMORY_SOURCES {
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lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif
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lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
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}
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# Canonical version-controlled Vivado IP customization
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set B210_IP_SOURCES {
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vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci
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}
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# Board/timing constraints
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set B210_CONSTRAINT_SOURCES {
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top/b200/b210.xdc
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}
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