90 lines
2.5 KiB
Systemverilog
90 lines
2.5 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfdc_info_memory
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//
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// Description:
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//
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// This module implements a memory that stores the RFDC information for the
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// RFDCs in the RFSoC. The memory is accessed via a controlport interface.
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// The memory is initialized by a device specfic pkg_rfdc_memory_content.
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// The memory is read only.
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//
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module rfdc_info_memory
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(
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// Clocks and Resets
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input logic clk,
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input logic rst,
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// request
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input logic [19:0] s_ctrlport_req_addr,
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input logic [ 3:0] s_ctrlport_req_byte_en,
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input logic [31:0] s_ctrlport_req_data,
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input logic s_ctrlport_req_rd,
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input logic s_ctrlport_req_wr,
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// response
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output logic s_ctrlport_resp_ack,
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output logic [31:0] s_ctrlport_resp_data,
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output logic [ 1:0] s_ctrlport_resp_status
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);
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`include "../../../../lib/rfnoc/core/ctrlport.vh"
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import rfdc_info_pkg::*;
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`ifdef X410
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import x410_rfdc_memory_content_pkg::*;
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`else
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import x440_rfdc_memory_content_pkg::*;
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`endif
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localparam int MEMORY_ADDR_SIZE = $clog2(NUM_ENTRIES);
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localparam int MEM_ADDR_INCR = 4;
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localparam int MEMORY_ADDR_LSB = $clog2(MEM_ADDR_INCR);
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// create memory with the RFDC information
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rfdc_memory_entry_t rfdc_memory [0:NUM_ENTRIES-1];
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initial begin
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// initialize memory
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for (int i = 0; i < NUM_ENTRIES; i++) begin
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rfdc_memory[i] = get_memory_entry(i);
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$info("Memory entry %d: %p", i, rfdc_memory[i]);
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end
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end
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// connect memory to the controlport interface
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always_ff @(posedge clk) begin
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if (rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= 32'b0;
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s_ctrlport_resp_status <= 2'b00;
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// handle reads
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end else if (s_ctrlport_req_rd) begin
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s_ctrlport_resp_ack <= 1'b1;
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// check overrange
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if (s_ctrlport_req_addr >= NUM_ENTRIES*MEM_ADDR_INCR) begin
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s_ctrlport_resp_data <= 32'b0;
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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end else begin
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s_ctrlport_resp_data <= rfdc_memory[s_ctrlport_req_addr[MEMORY_ADDR_LSB +: MEMORY_ADDR_SIZE]];
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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end
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// handle writes
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end else if (s_ctrlport_req_wr) begin
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// any other case
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endmodule
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