123 lines
4.4 KiB
Verilog
123 lines
4.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description
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// This code implements a parameterizable true dual port memory
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// (both ports can read and write). If an enable is not necessary
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// it may be tied off.
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//
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// Note
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// This module requires the ram_2port_impl.vh header file. The
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// header is included multiple times with different values of
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// the RAM_DIRECTIVE macro to create different implementations of the
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// RAM. An implementation is chosen in ram_2port based on the
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// user parameter for RAM_TYPE.
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// Mode: AUTOMATIC
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`define RAM_DIRECTIVE
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`define RAM_MOD_NAME ram_2port_impl_auto
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`include "ram_2port_impl.vh"
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`undef RAM_MOD_NAME
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`undef RAM_DIRECTIVE
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// Mode: REG
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`define RAM_DIRECTIVE (* ram_style = "registers" *)
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`define RAM_MOD_NAME ram_2port_impl_reg
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`include "ram_2port_impl.vh"
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`undef RAM_MOD_NAME
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`undef RAM_DIRECTIVE
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// Mode: LUTRAM
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`define RAM_DIRECTIVE (* ram_style = "distributed" *)
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`define RAM_MOD_NAME ram_2port_impl_lutram
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`include "ram_2port_impl.vh"
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`undef RAM_MOD_NAME
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`undef RAM_DIRECTIVE
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// Mode: BRAM
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`define RAM_DIRECTIVE (* ram_style = "block" *)
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`define RAM_MOD_NAME ram_2port_impl_bram
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`include "ram_2port_impl.vh"
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`undef RAM_MOD_NAME
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`undef RAM_DIRECTIVE
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// Mode: URAM
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`define RAM_DIRECTIVE (* ram_style = "ultra" *)
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`define RAM_MOD_NAME ram_2port_impl_uram
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`include "ram_2port_impl.vh"
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`undef RAM_MOD_NAME
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`undef RAM_DIRECTIVE
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module ram_2port #(
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parameter DWIDTH = 32, // Width of the memory block
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parameter AWIDTH = 9, // log2 of the depth of the memory block
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parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY}
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parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM}
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parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
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parameter INIT_FILE = "", // Optionally initialize memory with this file
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parameter INIT_VAL = {DWIDTH{1'b0}} // Optionally initialize output registers with this value and
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// memory will be filled with this value if INIT_FILE is empty
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) (
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input wire clka,
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input wire ena,
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input wire wea,
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input wire [AWIDTH-1:0] addra,
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input wire [DWIDTH-1:0] dia,
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output wire [DWIDTH-1:0] doa,
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input wire clkb,
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input wire enb,
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input wire web,
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input wire [AWIDTH-1:0] addrb,
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input wire [DWIDTH-1:0] dib,
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output wire [DWIDTH-1:0] dob
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);
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generate
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if (RAM_TYPE == "URAM")
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ram_2port_impl_uram #(
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.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
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.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
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) impl (
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.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
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);
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else if (RAM_TYPE == "BRAM")
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ram_2port_impl_bram #(
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.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
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.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
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) impl (
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.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
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);
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else if (RAM_TYPE == "LUTRAM")
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ram_2port_impl_lutram #(
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.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
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.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
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) impl (
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.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
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);
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else if (RAM_TYPE == "REG")
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ram_2port_impl_reg #(
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.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
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.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
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) impl (
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.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
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);
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else
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ram_2port_impl_auto #(
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.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
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.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
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) impl (
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.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
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);
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endgenerate
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endmodule
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