miegl/b210-k7-fpga
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Wade Fife eab91d8ed0 fpga: Update DRAM IO signatures 
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.


Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
2020-09-03 15:26:33 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
fpga: n3xx: Fix timeout for timekeeper registers
2020-08-19 12:28:22 -05:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
.gitignore
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2020-01-28 09:35:36 -08:00
build_n3xx.tcl
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2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
Makefile.n3xx.inc
fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin
2020-06-12 15:50:16 -05:00
mb_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_pins.xdc
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2020-01-28 09:35:36 -08:00
mb_timing.xdc
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2020-01-28 09:35:36 -08:00
n3xx_clocking.v
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2020-01-28 09:35:36 -08:00
n3xx_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
n3xx_db_fe_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_channel_wrapper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Fix White Rabbit images
2020-07-01 15:49:13 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
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2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
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2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
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2020-01-28 09:35:36 -08:00
n300_bist_image_core.v
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2020-01-28 09:35:36 -08:00
n300_bist_image_core.yml
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2020-01-28 09:35:36 -08:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.yml
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2020-01-28 09:35:36 -08:00
n300_static_router.hex
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2020-01-28 09:35:36 -08:00
n310_1ge.xdc
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n310_10ge.xdc
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2020-01-28 09:35:36 -08:00
n310_aurora.xdc
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n310_bist_image_core.v
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2020-01-28 09:35:36 -08:00
n310_bist_image_core.yml
Merge FPGA repository back into UHD repository
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n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
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2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
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2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n320_bist_image_core.v
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_bist_image_core.yml
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
n320: Double radio ingress buffer size
2020-08-12 15:17:48 -05:00
n320_rfnoc_image_core.yml
n320: Double radio ingress buffer size
2020-08-12 15:17:48 -05:00
n320_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00