adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: capture_sysref
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//
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// Description:
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//
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// Capture SYSREF and transfer it to the higher clock domain.
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// For X410, module incurs in 2 pll_ref_clk cycles + 1 rfdc_clk
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// cycle of delay. For X440, module synchronizes to each
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// pll_ref_clk and rfdc_clk separately, incurring in 2 cycles
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// for each clock.
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//
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// Parameters:
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//
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// DEVICE_TYPE : Type of device for which SYSREF is synchronized.
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//
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module capture_sysref (
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// Clocks
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input wire pll_ref_clk,
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input wire rfdc_clk,
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// SYSREF input and control
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input wire sysref_in, // Single-ended SYSREF (previously buffered)
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input wire enable_rclk, // Enables SYSREF output in the rfdc_clk domain.
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// Captured SYSREF outputs
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output wire sysref_out_pclk, // Debug output (Domain: pll_ref_clk).
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output wire sysref_out_rclk // RFDC output (Domain: rfdc_clk).
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);
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(* ASYNC_REG = "TRUE" *) reg sysref_pclk_ms = 1'b0;
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reg sysref_pclk = 1'b0;
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reg sysref_rclk = 1'b0;
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// Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
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// in case static timing isn't met so as not to destroy downstream logic.
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always @ (posedge pll_ref_clk) begin
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sysref_pclk_ms <= sysref_in;
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sysref_pclk <= sysref_pclk_ms;
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end
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assign sysref_out_pclk = sysref_pclk;
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// Transfer to faster clock which is edge-aligned with the pll_ref_clk.
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always @ (posedge rfdc_clk) begin
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if (enable_rclk) begin
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sysref_rclk <= sysref_pclk;
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end else begin
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sysref_rclk <= 1'b0;
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end
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end
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assign sysref_out_rclk = sysref_rclk;
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endmodule
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