Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
229 lines
8.6 KiB
VHDL
229 lines
8.6 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: rf_nco_reset
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--
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-- Description:
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--
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-- This entity has the logic needed to synchronously reset the NCO inside the
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-- RF section.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity rf_nco_reset is
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port(
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-- AXI-lite clock used for RFDC configuration.
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ConfigClk : in std_logic;
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-- Radio clock used in the converter data path.
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DataClk : in std_logic;
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-- PL SYSREF
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dSysref : in std_logic;
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--Strobe dNcoResetEn for one DataClk cycle to initiate NCO reset.
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dStartNcoReset : in std_logic;
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---------------------------------------------------------------------------
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-- NCO reset controls and status
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---------------------------------------------------------------------------
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-- Port naming convention:
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-- cDac<Tile Number><Converter Number><signal name>
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-- cAdc<Tile Number><Converter Number><signal name>
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-----------------------------------
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-- DAC Tile 228
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-----------------------------------
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-- DAC common NCO update controls and status.
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cDac0xNcoUpdateBusy : in std_logic_vector(1 downto 0);
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cDac0xNcoUpdateReq : out std_logic := '0';
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cDac0xSysrefIntGating : out std_logic := '0';
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cDac0xSysrefIntReenable : out std_logic := '0';
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-----------------------------------
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-- DAC Tile 229
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-----------------------------------
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-- DAC common NCO update controls and status.
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cDac1xNcoUpdateBusy : in std_logic;
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cDac1xNcoUpdateReq : out std_logic := '0';
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-----------------------------------
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--ADC Tile 224
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-----------------------------------
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-- ADC common NCO update controls and status.
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cAdc0xNcoUpdateBusy : in std_logic;
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cAdc0xNcoUpdateReq : out std_logic := '0';
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-----------------------------------
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--ADC Tile 226
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-----------------------------------
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-- ADC common NCO update controls and status.
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cAdc2xNcoUpdateBusy : in std_logic;
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cAdc2xNcoUpdateReq : out std_logic := '0';
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-- NCO reset can be initiated only when cNcoPhaseRst is set to '1' and
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-- cNcoUpdateEn = 0x20. The FSM in this entity will set these values when
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-- an NCO reset is initiated during synchronization. These ports are common
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-- for all the converters. So, we will fan these signals out to each
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-- converter outside this entity.
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cNcoPhaseRst : out std_logic := '1';
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cNcoUpdateEn : out std_logic_vector(5 downto 0) := "100000";
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-- NCO reset status back to the user.
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dNcoResetDone : out std_logic := '0'
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);
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end rf_nco_reset;
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architecture RTL of rf_nco_reset is
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-- State machine to sequence NCO reset across different RFDC tiles.
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type ResetState_t is (Idle, ReqGating, CheckGating, CheckUpdateDone,
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CheckResetDone, ResetDone);
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signal cResetState : ResetState_t := Idle;
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signal dNcoResetDone_ms, cNcoResetDone : std_logic := '0';
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signal dStartNcoResetReg, cStartNcoReset_ms, cStartNcoReset : std_logic := '0';
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signal cSysref_ms, cSysref, cSysrefDlyd : std_logic := '0';
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signal cSysrefIntGating, dSysrefIntGating_ms,
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dSysrefIntGating : std_logic := '0';
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begin
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-- NCO start signal from the user is a one DataClk cycle strobe. In this
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-- process, we register the NCO start request from the user. This NCO start
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-- request register is cleared after the NCO reset sequence is initiated. We
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-- used the signal used to gate SYSREF to clear this register.
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RegNcoStart: process(DataClk)
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begin
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if rising_edge(DataClk) then
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dSysrefIntGating_ms <= cSysrefIntGating;
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dSysrefIntGating <= dSysrefIntGating_ms;
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if dSysrefIntGating = '1' then
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dStartNcoResetReg <= '0';
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elsif dStartNcoReset = '1' then
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dStartNcoResetReg <= '1';
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end if;
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end if;
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end process RegNcoStart;
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-- Irrespective of when NCO reset strobe is issued by the user, we need to
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-- initiate NCO reset only on the rising edge of SYSREF. This is because, we
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-- have to complete the reset within a SYSREF period.
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ConfigClkCross: process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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cSysref_ms <= dSysref;
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cSysref <= cSysref_ms;
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cSysrefDlyd <= cSysref;
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cStartNcoReset_ms <= dStartNcoResetReg;
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cStartNcoReset <= cStartNcoReset_ms;
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end if;
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end process ConfigClkCross;
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-- These signals can be set to a constant value as NCO phase reset is only
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-- initiated by *NcoUpdateReq signal.
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cNcoPhaseRst <= '1';
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cNcoUpdateEn <= "100000";
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-- ! STATE MACHINE STARTUP !
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-- The state machine starts in Idle state and does not change state until
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-- cStartNcoReset is set to '1'. cStartNcoReset signal and cSysref are based
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-- of ConfigClock so changing state from Idle cannot go metastable. State
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-- machine to initiate NCO reset on all enabled RFDC tiles. This state
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-- machine was written based of the information provided in "NCO frequency
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-- hopping" section in PG269 (v2.2). We use multi-mode for NCO reset.
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ResetFsm: process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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cResetState <= Idle;
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cNcoResetDone <= '0';
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cDac0xNcoUpdateReq <= '0';
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cSysrefIntGating <= '0';
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cDac0xSysrefIntReenable <= '0';
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cDac1xNcoUpdateReq <= '0';
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cAdc0xNcoUpdateReq <= '0';
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cAdc2xNcoUpdateReq <= '0';
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case cResetState is
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-- Stay in this state until NCO reset sequence is initiated. NCO reset
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-- is initiated only on the rising edge of SYSREF.
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when Idle =>
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if cSysref = '1' and cSysrefDlyd = '0' and cStartNcoReset = '1' then
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cResetState <= ReqGating;
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cSysrefIntGating <= '1';
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end if;
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-- When NCO reset is initiated, gate the RFDC internal SYSREF. To gate
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-- internal SYSREF set cSysrefIntGating to '1'. To request NCO reset
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-- strobe cDac0xNcoUpdateReq for one ConfigClk period. At this point,
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-- we can only request NCO reset for RF-DAC tile 228.
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when ReqGating =>
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cResetState <= CheckGating;
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cDac0xNcoUpdateReq <= '1';
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cSysrefIntGating <= '1';
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-- Since we are gating SYSREF inside RFDC, we need to wait until SYSREF
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-- is gated internally. RFDC sets cDac0xNcoUpdateBusy[0] to '1' when
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-- SYSREF is gated. cDac0xNcoUpdateBusy[1] is also set to '1' to
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-- indicate that NCO reset is still in progress. After the SYSREF is
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-- gated request NCO reset on all other converter tiles.
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when CheckGating =>
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cSysrefIntGating <= '1';
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cResetState <= CheckGating;
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if cDac0xNcoUpdateBusy = "11" then
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cResetState <= CheckUpdateDone;
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cDac1xNcoUpdateReq <= '1';
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cAdc0xNcoUpdateReq <= '1';
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cAdc2xNcoUpdateReq <= '1';
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end if;
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-- In this state, we check if the RFDC block is ready for NCO reset.
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-- This check is done using the *Busy signal from RFDC. Once RFDC is
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-- ready for NCO reset, disable internal SYSREF gating.
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when CheckUpdateDone =>
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cSysrefIntGating <= '1';
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cResetState <= CheckUpdateDone;
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if cDac0xNcoUpdateBusy = "10" and cAdc0xNcoUpdateBusy = '0' and
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cAdc2xNcoUpdateBusy = '0' and cDac1xNcoUpdateBusy = '0' and
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cSysref = '1' and cSysrefDlyd = '0' then
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cDac0xSysrefIntReenable <= '1';
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cResetState <= CheckResetDone;
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end if;
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-- NCO reset is done when cDac0xNcoUpdateBusy[1] is set to '0'. RFDC is
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-- programmed from software to reset the NCO on a SYSREF rising edge.
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when CheckResetDone =>
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cSysrefIntGating <= '1';
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cResetState <= CheckResetDone;
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if cDac0xNcoUpdateBusy = "00" then
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cResetState <= ResetDone;
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end if;
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-- Wait in this state until another NCO reset request is issued.
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when ResetDone =>
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cNcoResetDone <= '1';
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cResetState <= ResetDone;
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if cSysref = '1' and cSysrefDlyd = '0' and cStartNcoReset = '1' then
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cResetState <= ReqGating;
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cSysrefIntGating <= '1';
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end if;
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end case;
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end if;
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end process ResetFsm;
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cDac0xSysrefIntGating <= cSysrefIntGating;
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-- Move the NCO reset done status to DataClk domain.
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DataClkCrossing: process(DataClk)
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begin
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if rising_edge(DataClk) then
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dNcoResetDone_ms <= cNcoResetDone;
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dNcoResetDone <= dNcoResetDone_ms;
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end if;
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end process DataClkCrossing;
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end RTL;
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