61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
81 lines
2.4 KiB
Verilog
81 lines
2.4 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: dac_gearbox_4x2
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//
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// Description:
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//
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// Gearbox DAC data from 4 SPC to 2 SPC and corresponding 2x clock to 1x
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// clock.
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// This module incurs in one clk1x cycle of delay on the data and valid
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// signals from input on the 1x domain to output on the 2x domain.
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//
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`default_nettype none
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module dac_gearbox_4x2 (
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input wire clk1x,
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input wire reset_n_1x,
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// Data is _presumed_ to be packed [Q3,I3,Q2,I2,Q1,I1,Q0,I0]
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input wire [127:0] data_in_1x,
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input wire valid_in_1x,
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output wire ready_out_1x,
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input wire clk2x,
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// Data is packed [Q1,I1,Q0,I0] (I in LSBs)
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output wire [ 63:0] data_out_2x,
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output wire valid_out_2x
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);
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// Re-create the 1x clock in the 2x domain to produce a deterministic
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// crossing.
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reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
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reg [127:0] data_in_2x_dly0 = 128'b0, data_in_2x_dly1 = 32'b0;
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reg [63 :0] data_2x_dly = 64'b0;
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// Create a toggle in the 1x clock domain (clock divider /2).
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always @(posedge clk1x or negedge reset_n_1x) begin
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if ( ! reset_n_1x) begin
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toggle_1x <= 1'b0;
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end else begin
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toggle_1x <= ! toggle_1x;
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end
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end
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// Transfer the toggle from the 1x to the 2x domain. Delay the toggle in the
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// 2x domain by one cycle and compare it to the non-delayed version. When
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// they differ, push data_in[63:0] onto the output. When they match, push
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// [127:64] onto the output.
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//
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// It is safe to not reset this domain because all of the input signals will
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// be cleared by the 1x reset. Safe default values are assigned to all these
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// registers.
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always @(posedge clk2x) begin
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toggle_2x <= toggle_1x;
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toggle_2x_dly <= toggle_2x;
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data_in_2x_dly0 <= data_in_1x;
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data_in_2x_dly1 <= data_in_2x_dly0 ;
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data_2x_dly <= 64'b0;
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if (valid_2x) begin
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data_2x_dly <= data_in_2x_dly1[127:64];
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if (toggle_2x != toggle_2x_dly) begin
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data_2x_dly <= data_in_2x_dly0[63:0];
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end
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end
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// Valid is simply a transferred version of the 1x clock's valid. Delay it
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// one more cycle to align outputs.
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valid_2x <= valid_in_1x;
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valid_dly_2x <= valid_2x;
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end
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assign valid_out_2x = valid_dly_2x;
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assign data_out_2x = data_2x_dly;
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assign ready_out_1x = 1'b1;
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endmodule
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`default_nettype wire
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