61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
84 lines
2.5 KiB
VHDL
84 lines
2.5 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: ddc_saturate
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--
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-- Description:
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--
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-- Saturation logic for reducing 2x24 bit words to 2x16 bit words. See
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-- comments below for full description.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity ddc_saturate is
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port(
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Clk : in std_logic;
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cDataIn : in std_logic_vector(47 downto 0); -- [Q,I] (I in LSBs)
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cDataValidIn : in std_logic;
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cDataOut : out std_logic_vector(31 downto 0); -- [Q,I] (I in LSBs)
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cDataValidOut : out std_logic
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);
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end ddc_saturate;
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architecture RTL of ddc_saturate is
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signal cDataOutI : std_logic_vector(15 downto 0) := (others => '0');
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signal cDataOutQ : std_logic_vector(15 downto 0) := (others => '0');
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begin
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-----------------------------------------------------------------------------
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-- Saturation
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--
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-- The output of the Xilinx FIR Compiler has already been rounded on the LSB
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-- side, but hasn't been saturated on the MSB side.
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-- Coefficients = 18 bit, 1 integer bit (1.17)
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-- Data In = 16 bits, 1 integer bit (1.15)
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-- 1.17 * 1.15 = 2.32, and the Xilinx FIR core rounds to 2.15
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-- Data Out = 17 bits, 2 integer bits (2.15), with 17 LSBs already rounded
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-- off inside the FIR core.
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-- We need to manually saturate the 2.15 number back to a 1.15 number
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--
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-- If 2 MSBs = 00, output <= input without MSB, e.g. positive number < 1
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-- If 2 MSBs = 01, output <= 0.111111111111111, e.g. positive number >= 1
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-- If 2 MSBs = 10, output <= 1.000000000000000, e.g. negative number < -1
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-- If 2 MSBs = 11, output <= input without MSB, e.g. negative number >= -1
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-----------------------------------------------------------------------------
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Saturation:
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process(Clk)
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begin
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if rising_edge(Clk) then
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-- Pipeline data valid to match the data
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cDataValidOut <= cDataValidIn;
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-- I, from cDataIn(16 downto 0)
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if cDataIn(16 downto 15) = "01" then
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cDataOutI <= "0111111111111111";
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elsif cDataIn(16 downto 15) = "10" then
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cDataOutI <= "1000000000000000";
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else
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cDataOutI <= cDataIn(15 downto 0);
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end if;
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-- Q, from cDataIn(40 downto 24)
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if cDataIn(40 downto 39) = "01" then
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cDataOutQ <= "0111111111111111";
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elsif cDataIn(40 downto 39) = "10" then
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cDataOutQ <= "1000000000000000";
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else
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cDataOutQ <= cDataIn(39 downto 24);
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end if;
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end if;
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end process Saturation;
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cDataOut <= cDataOutQ & cDataOutI;
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end RTL;
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