61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
121 lines
4.3 KiB
Verilog
121 lines
4.3 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: adc_gearbox_2x1
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//
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// Description:
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//
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// Gearbox ADC data from 2 SPC to 1 SPC and corresponding 2x clock to 1x
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// clock. Also implement data swapping to format packets to fit the FIR
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// filter input requirements.
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//
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// This modules incurs one clk1x cycle of delay on the data and valid signals
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// from input on the 1x domain to output on the 2x domain.
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//
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`default_nettype none
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module adc_gearbox_2x1 (
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input wire clk1x,
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input wire reset_n_1x,
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// Data is _presumed_ to be packed [Sample1, Sample0] (Sample0 in LSBs).
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input wire [31:0] adc_q_in_1x,
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input wire [31:0] adc_i_in_1x,
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input wire valid_in_1x,
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// De-assert enable_1x to clear the data synchronously from this module.
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input wire enable_1x,
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input wire clk2x,
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// Data is packed [Q,I] (I in LSBs) when swap_iq_1x is '0'.
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input wire swap_iq_2x,
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output wire [31:0] adc_out_2x,
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output wire valid_out_2x
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);
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// Re-create the 1x clock in the 2x domain to produce a deterministic
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// crossing.
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reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
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reg [31:0] data_out_2x = 32'b0, adc_q_data_in_2x = 32'b0, adc_i_data_in_2x = 32'b0;
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// Create a toggle in the 1x clock domain (clock divider /2).
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always @(posedge clk1x or negedge reset_n_1x) begin
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if ( ! reset_n_1x) begin
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toggle_1x <= 1'b0;
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end else begin
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toggle_1x <= ! toggle_1x;
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end
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end
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// clk1x and clk2x are nominally aligned on their rising edges, but clk2x is
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// more heavily loaded, which results in a later arrival time. That late
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// arrival causes large estimated hold violations after place. The Ultrafast
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// method (UG 949) suggests fixing post-place hold violations that are worse
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// than -0.5 ns.
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// Resampling 1x signals on the falling edge of clk2x provides nominally half
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// a period of setup and half a period of hold. The late arrival of clk2x
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// shifts some of that margin away from hold slack and into setup slack.
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reg toggle_2x_fall = 1'b0;
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reg [31:0] adc_q_in_2x_fall = 32'b0;
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reg [31:0] adc_i_in_2x_fall = 32'b0;
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reg valid_in_2x_fall = 1'b0;
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reg enable_2x_fall = 1'b0;
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always @(negedge clk2x) begin
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toggle_2x_fall <= toggle_1x;
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adc_q_in_2x_fall <= adc_q_in_1x;
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adc_i_in_2x_fall <= adc_i_in_1x;
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valid_in_2x_fall <= valid_in_1x;
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enable_2x_fall <= enable_1x;
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end
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// Transfer the toggle from the 1x to the 2x domain. Delay the toggle in the
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// 2x domain by one cycle and compare it to the non-delayed version. When
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// they differ, push data_in[15:0] onto the output. When the match, push
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// [31:16] onto the output. The datasheet is unclear on the exact
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// implementation.
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//
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// It is safe to not reset this domain because all of the input signals will
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// be cleared by the 1x reset. Safe default values are assigned to all these
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// registers.
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always @(posedge clk2x) begin
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toggle_2x <= toggle_2x_fall;
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toggle_2x_dly <= toggle_2x;
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adc_q_data_in_2x <= adc_q_in_2x_fall;
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adc_i_data_in_2x <= adc_i_in_2x_fall;
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// Place Q in the MSBs, I in the LSBs by default, unless swapped = 1.
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if (valid_2x) begin
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if (swap_iq_2x) begin
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if (toggle_2x != toggle_2x_dly) begin
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data_out_2x[31:16] <= adc_i_data_in_2x[15:0];
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data_out_2x[15: 0] <= adc_q_data_in_2x[15:0];
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end else begin
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data_out_2x[31:16] <= adc_i_data_in_2x[31:16];
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data_out_2x[15: 0] <= adc_q_data_in_2x[31:16];
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end
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end else begin
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if (toggle_2x != toggle_2x_dly) begin
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data_out_2x[31:16] <= adc_q_data_in_2x[15:0];
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data_out_2x[15: 0] <= adc_i_data_in_2x[15:0];
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end else begin
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data_out_2x[31:16] <= adc_q_data_in_2x[31:16];
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data_out_2x[15: 0] <= adc_i_data_in_2x[31:16];
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end
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end
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end else begin
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data_out_2x <= 32'b0;
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end
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// Valid is simply a transferred version of the 1x clock's valid. Delay it
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// one more cycle to align outputs.
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valid_2x <= valid_in_2x_fall && enable_2x_fall;
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valid_dly_2x <= valid_2x;
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end
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assign adc_out_2x = data_out_2x;
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assign valid_out_2x = valid_dly_2x;
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endmodule
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`default_nettype wire
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