Files
b210-k7-fpga/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl
T
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00

15 lines
902 B
Tcl

set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd
read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd