Sam O'Brien
1b952d33df
Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
1211 lines
47 KiB
Systemverilog
1211 lines
47 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_100g
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//
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// Description: Wrapper for the Xilinx 100G mac
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module eth_100g #(
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logic PAUSE_EN = 1,
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logic [15:0] PAUSE_QUANTA = 16'hFFFF,
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logic [15:0] PAUSE_REFRESH = 16'hFFFF
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)(
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// Resets
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input logic areset,
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// Clock for misc stuff
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input logic clk100,
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// Low jitter refclk
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input logic refclk_p,
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input logic refclk_n,
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// RX Clk for output
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output logic rx_rec_clk_out,
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// MGT high-speed IO
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output logic[3:0] tx_p,
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output logic[3:0] tx_n,
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input logic[3:0] rx_p,
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input logic[3:0] rx_n,
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// Data port
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output logic mgt_clk,
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output logic mgt_rst,
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input logic mgt_pause_req,
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// Interface clocks for mgt_tx and mgt_rx are NOT used (logic uses mgt_clk)
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AxiStreamIf.slave mgt_tx,
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AxiStreamIf.master mgt_rx,
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// Axi port
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AxiLiteIf.slave mgt_axil,
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// Misc
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output logic [31:0] phy_status,
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input logic [31:0] mac_ctrl,
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output logic [31:0] mac_status,
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output logic phy_reset,
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output logic link_up
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);
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logic tx_ovfout;
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logic tx_unfout;
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logic stat_rx_aligned;
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logic stat_auto_config_done;
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logic stat_auto_config_done_bclk;
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logic usr_tx_reset;
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logic usr_rx_reset;
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// Hierarchical reference (Xilinx says it will synthesize)
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// eth_100g_bd_i/cmac_usplus_0/gt_rxrecclkout}
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assign rx_rec_clk_out = eth_100g_bd_i.cmac_usplus_0.gt_rxrecclkout[0];
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//status registers
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always_comb begin
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phy_status = 0;
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phy_status[0] = usr_tx_reset;
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phy_status[1] = usr_rx_reset;
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end
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logic [8:0] pause_mask; // from mac ctl register bits 24:16
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always_ff @(posedge mgt_clk) begin : mac_status_reg
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if (mgt_rst) begin
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mac_status <= 0;
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end else begin
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mac_status[0] <= mac_status[0] || tx_ovfout;
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mac_status[1] <= mac_status[1] || tx_unfout;
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mac_status[2] <= stat_rx_aligned;
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mac_status[3] <= mac_status[3] || (!mgt_rx.tready && mgt_rx.tvalid);
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mac_status[4] <= stat_auto_config_done;
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mac_status[24:16] <= pause_mask;
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end
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end
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// synthesis translate_off
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//extra simulation checks
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localparam USE_MAC_CHECKS = 1;
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if (USE_MAC_CHECKS) begin
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always_ff @(posedge mgt_rx.clk) begin : check_no_holdoff
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if (!mgt_rx.rst) begin
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if (!mgt_rx.tready && mgt_rx.tvalid) begin
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$fatal(1,"MAC RX can't hold off the MAC");
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end
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assert(tx_ovfout==0) else
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$fatal(1,"MAC TX had an overflow!");
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assert(tx_unfout==0) else
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$fatal(1,"MAC TX had an underflow!");
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end
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end
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end
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initial begin
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assert (mgt_tx.DATA_WIDTH == 512) else
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$fatal(1, "mgt_rx.DATA_WIDTH must be 512");
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// $clog2(512/8)+1
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assert (mgt_rx.USER_WIDTH == 7) else
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$fatal(1, "mgt_rx.USER_WIDTH must be 7");
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assert (mgt_tx.TDATA == 1) else
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$fatal(1, "mgt_tx.TDATA must be enabled");
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assert (mgt_tx.TUSER == 1) else
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$fatal(1, "mgt_tx.TUSER must be enabled");
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assert (mgt_tx.TKEEP == 1) else
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$fatal(1, "mgt_tx.TKEEP must be enabled");
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assert (mgt_tx.TLAST == 1) else
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$fatal(1, "mgt_tx.TLAST must be enabled");
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assert (mgt_rx.DATA_WIDTH == 512) else
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$fatal(1, "mgt_rx.DATA_WIDTH must be 512");
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// $clog2(512/8)+1
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assert (mgt_rx.USER_WIDTH == 7) else
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$fatal(1, "mgt_rx.DATA_WIDTH must be 7");
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assert (mgt_rx.TDATA == 1) else
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$fatal(1, "mgt_rx.TDATA must be enabled");
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assert (mgt_rx.TUSER == 1) else
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$fatal(1, "mgt_rx.TUSER must be enabled");
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assert (mgt_rx.TKEEP == 0) else
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$fatal(1, "mgt_rx.TKEEP must not be enabled");
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assert (mgt_rx.TLAST == 1) else
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$fatal(1, "mgt_rx.TLAST must be enabled");
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end
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// synthesis translate_on
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AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0))
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eth100g_tx(mgt_clk,mgt_rst);
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AxiStreamIf #(.DATA_WIDTH(512),.USER_WIDTH(7),.TKEEP(0))
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eth100g_rx(mgt_clk,mgt_rst);
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logic mgt_tx_idle;
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logic mgt_tx_pause;
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always_comb begin
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eth100g_tx.tdata = mgt_tx.tdata;
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eth100g_tx.tuser = 0;
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eth100g_tx.tkeep = mgt_tx.tkeep;
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eth100g_tx.tvalid = mgt_tx.tvalid && !mgt_tx_pause;
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eth100g_tx.tlast = mgt_tx.tlast;
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mgt_tx.tready = eth100g_tx.tready && !mgt_tx_pause;
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end
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always_comb begin
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mgt_rx.tdata = eth100g_rx.tdata;
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mgt_rx.tuser = eth100g_rx.tuser;
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mgt_rx.tuser[mgt_rx.USER_WIDTH-1] = // assign error bit [MSB]
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// CRC failure
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eth100g_rx.tuser[mgt_rx.USER_WIDTH-1] ||
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// Missed a DATA word.
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mgt_rx.tvalid && !mgt_rx.tready;
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mgt_rx.tkeep = eth100g_rx.tkeep;
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mgt_rx.tvalid = eth100g_rx.tvalid;
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mgt_rx.tlast = eth100g_rx.tlast;
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// The MAC ignores hold off. Data must be consumed every clock it is valid.
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// eth100g_rx.tready = mgt_rx.tready;
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end
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// This is a heavily replicated signal, add some pipeline
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// to it to make it easier to spread out
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logic mgt_rst_0;
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// Flow control signals
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// 0-7 map to PCP codes 0-7. 8 is a global pause request
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logic [8:0] stat_rx_pause_req ;
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logic [8:0] ctl_tx_pause_req ; // drive for at least 16 clocks
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logic ctl_tx_resend_pause; // resend the pause request (tying this high forces a spam of resend requests)
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// QuantaPeriod is 512 bit times or 5.12 ns
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// resend pause requests so (quanta*QuantaPeriod)/(refresh*QuantaPeriod) is the percentage of BW that gets through.
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// pause_mask is part of the mac_ctrl register
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always_comb begin
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ctl_tx_resend_pause = 0;
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ctl_tx_pause_req = '0;
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if (mgt_pause_req) begin
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ctl_tx_pause_req = pause_mask;
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end
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end
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logic mgt_tx_pause_req;
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assign mgt_tx_pause_req = (pause_mask & stat_rx_pause_req) != 0;
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always_ff @(posedge mgt_clk,posedge areset) begin : reset_timing_dff
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if (areset) begin
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mgt_rst_0 <= 1'b1;
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mgt_rst <= 1'b1;
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mgt_tx_pause <= 1'b0;
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mgt_tx_idle <= 1'b1;
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end else begin
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mgt_rst_0 <= !link_up;
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mgt_rst <= mgt_rst_0;
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//idle until a valid sets
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if (mgt_tx_idle) begin
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if (!eth100g_tx.tvalid) begin
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mgt_tx_pause <= mgt_tx_pause_req;
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end else begin
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// one clock packet
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if (eth100g_tx.tvalid && eth100g_tx.tlast && eth100g_tx.tready) begin
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mgt_tx_idle <= 1;
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mgt_tx_pause <= mgt_tx_pause_req;
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end else begin
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mgt_tx_idle <= 0;
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end
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end
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//set idle if end of packet is accepted
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end else if (eth100g_tx.tvalid && eth100g_tx.tlast && eth100g_tx.tready) begin
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mgt_tx_idle <= 1;
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mgt_tx_pause <= mgt_tx_pause_req;
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end
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end
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end
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always_comb phy_reset = usr_tx_reset || usr_rx_reset;
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always_comb link_up = stat_rx_aligned && !phy_reset;
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// resets stat counts and moves the total to the readable version.
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localparam PM_COUNT = 40000;
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logic pm_tick = 0;
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logic [15:0] pm_tick_count;
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always_ff @(posedge mgt_axil.clk) begin : pm_tick_counter
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if (mgt_axil.rst) begin
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pm_tick_count = 0;
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pm_tick = 0;
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end else begin
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if (pm_tick_count == PM_COUNT-1) begin
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pm_tick_count = 0;
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pm_tick = 1;
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end else begin
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pm_tick_count = pm_tick_count+1;
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pm_tick = 0;
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end
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end
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end
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`include "../../../../lib/axi4lite_sv/axi_lite.vh"
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AxiLiteIf_v #(.DATA_WIDTH(mgt_axil.DATA_WIDTH),.ADDR_WIDTH(32))
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mgt_axil_v(.clk(mgt_axil.clk),.rst(mgt_axil.rst));
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localparam AUTO_CONNECT=1;
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// When enabled the port will automatically attempt to connect to an Ethernet partner
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// without requiring any action from SW. If it is not defined, SW will have to perform
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// a similar set of writes. Xilinx publishes a driver for the MAC, that we could associate.
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// The sequence of writes was taken from the CMAC example, without any deep knowledge
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// of what the standard Ethernet connection protocol is.
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// Inject writes to perform connection in between other SW writes to read the mac.
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if (AUTO_CONNECT) begin : yes_auto_connect
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// defined in https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
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// pg 187
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localparam CONFIGURATION_TX_REG1 = 32'h000C;
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localparam ctl_tx_ctl_enable = 0;
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localparam ctl_tx_ctl_tx_send_lfi = 3;
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localparam ctl_tx_ctl_tx_send_rfi = 4;
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localparam ctl_tx_ctl_tx_send_idle = 5;
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localparam ctl_tx_ctl_test_pattern = 16;
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localparam CONFIGURATION_RX_REG1 = 32'h0014;
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localparam ctl_rx_ctl_enable = 0;
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localparam ctl_rx_ctl_rx_force_resync = 7;
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localparam ctl_rx_ctl_test_pattern = 8;
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localparam RSFEC_CONFIG_INDICATION_CORRECTION = 32'h1000;
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localparam rs_fec_in_ctl_rx_rsfec_enable_correction = 0;
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localparam rs_fec_in_ctl_rx_rsfec_enable_indication = 1;
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localparam rs_fec_in_ctl_rsfec_ieee_error_indication_mode = 2;
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localparam RSFEC_CONFIG_ENABLE = 32'h107C;
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localparam rs_fec_in_ctl_rx_rsfec_enable = 0;
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localparam rs_fec_in_ctl_tx_rsfec_enable = 1;
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// Extra configuration for Pause Frames (CMAC guide Pg 210)
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//0x0084 : 32'h00003DFF [CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1]
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//0x0088 : 32'h0001C631 [CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2]
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//0x0048 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1]
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//0x004C : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2]
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//0x0050 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3]
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//0x0054 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4]
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//0x0058 : 32'h0000FFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5]
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//0x0034 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1]
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//0x0038 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2]
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//0x003C : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3]
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//0x0040 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4]
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//0x0044 : 32'h0000FFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5]
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//0x0030 : 32'h000001FF [CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1]
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localparam CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1 = 32'h0084;
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//3DFF - 0011 1101 1111 1111
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localparam ctl_rx_pause_en = 0; // 9 bits
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localparam ctl_rx_enable_gcp = 10;
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localparam ctl_rx_enable_pcp = 11;
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localparam ctl_rx_enable_gpp = 12;
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localparam ctl_rx_enable_ppp = 13;
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localparam ctl_rx_pause_ack = 23; // 8 bits
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localparam CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2 = 32'h0088;
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//1C631 - 0001 1100 0110 0011 0001
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localparam ctl_rx_check_mcast_gcp = 0; //1
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localparam ctl_rx_check_ucast_gcp = 1;
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localparam ctl_rx_check_sa_gcp = 2;
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localparam ctl_rx_check_etype_gcp = 3;
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localparam ctl_rx_check_opcode_gcp = 4; //1
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localparam ctl_rx_check_mcast_pcp = 5; //1
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localparam ctl_rx_check_ucast_pcp = 6;
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localparam ctl_rx_check_sa_pcp = 7;
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localparam ctl_rx_check_etype_pcp = 8;
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localparam ctl_rx_check_opcode_pcp = 9; //1
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localparam ctl_rx_check_mcast_gpp = 10; //1
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localparam ctl_rx_check_ucast_gpp = 11;
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localparam ctl_rx_check_sa_gpp = 12;
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localparam ctl_rx_check_etype_gpp = 13;
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localparam ctl_rx_check_opcode_gpp = 14; //1
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localparam ctl_rx_check_opcode_ppp = 15; //1
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localparam ctl_rx_check_mcast_ppp = 16; //1
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localparam ctl_rx_check_ucast_ppp = 17;
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localparam ctl_rx_check_sa_ppp = 18;
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localparam ctl_rx_check_etype_ppp = 19;
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localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 = 32'h0048;
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localparam ctl_tx_pause_quanta0 = 0;
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localparam ctl_tx_pause_quanta1 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 = 32'h004C;
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localparam ctl_tx_pause_quanta2 = 0;
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localparam ctl_tx_pause_quanta3 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 = 32'h0050;
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localparam ctl_tx_pause_quanta4 = 0;
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localparam ctl_tx_pause_quanta5 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 = 32'h0054;
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localparam ctl_tx_pause_quanta6 = 0;
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localparam ctl_tx_pause_quanta7 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5 = 32'h0058;
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localparam ctl_tx_pause_quanta8 = 0;
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localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1 = 32'h0034;
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localparam ctl_tx_pause_refresh_timer0 = 0;
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localparam ctl_tx_pause_refresh_timer1 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2 = 32'h0038;
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localparam ctl_tx_pause_refresh_timer2 = 0;
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localparam ctl_tx_pause_refresh_timer3 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3 = 32'h003C;
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localparam ctl_tx_pause_refresh_timer4 = 0;
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localparam ctl_tx_pause_refresh_timer5 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4 = 32'h0040;
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localparam ctl_tx_pause_refresh_timer6 = 0;
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localparam ctl_tx_pause_refresh_timer7 = 16;
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localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5 = 32'h0044;
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localparam ctl_tx_pause_refresh_timer8 = 0;
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localparam CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1 = 32'h0030;
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// 1FF
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localparam ctl_tx_pause_enable = 0; // 9 bits
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AxiLiteIf #(.DATA_WIDTH(mgt_axil.DATA_WIDTH),.ADDR_WIDTH(32))
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auto_axil(.clk(mgt_axil.clk),.rst(mgt_axil.rst));
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typedef enum logic [4:0] {
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ST_RESET = 5'd0,
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ST_WR_CONFIGURATION_TX_REG1_IDLE = 5'd1,
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ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION = 5'd2,
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ST_WR_RSFEC_CONFIG_ENABLE = 5'd3,
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ST_WR_CONFIGURATION_RX_REG1 = 5'd4,
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ST_WAIT = 5'd5,
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ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE = 5'd6,
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ST_READY = 5'd7,
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// EXTRA PAUSE WRITES
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ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1 = 5'd8,
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ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2 = 5'd9,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 = 5'd10,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 = 5'd11,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 = 5'd12,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 = 5'd13,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5 = 5'd14,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1 = 5'd15,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2 = 5'd16,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3 = 5'd17,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4 = 5'd18,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5 = 5'd19,
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ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1 = 5'd20
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} auto_connect_state_t;
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auto_connect_state_t auto_connect_state = ST_RESET;
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logic auto_rst0, auto_rst1, auto_rst2, auto_rst3;
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logic mgt_axil_in_progress;
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logic w_req, aw_req;
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logic phy_reset_bclk,stat_rx_aligned_bclk;
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logic auto_enable;
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synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) phy_reset_sync_i (
|
|
.clk(mgt_axil.clk), .rst(1'b0), .in(phy_reset), .out(phy_reset_bclk)
|
|
);
|
|
|
|
synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) rx_aligned_sync_i (
|
|
.clk(mgt_axil.clk), .rst(1'b0), .in(stat_rx_aligned), .out(stat_rx_aligned_bclk)
|
|
);
|
|
|
|
synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) auto_config_done_sync_i (
|
|
.clk(mgt_clk), .rst(1'b0), .in(stat_auto_config_done_bclk), .out(stat_auto_config_done)
|
|
);
|
|
|
|
|
|
synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) auto_enable_sync_i (
|
|
.clk(mgt_axil.clk), .rst(1'b0), .in(mac_ctrl[0]), .out(auto_enable)
|
|
);
|
|
|
|
synchronizer #( .STAGES(2), .WIDTH(9), .INITIAL_VAL(9'h100) ) pause_mask_sync_i (
|
|
.clk(mgt_clk), .rst(1'b0), .in(mac_ctrl[24:16]), .out(pause_mask)
|
|
);
|
|
|
|
|
|
always_ff @(posedge mgt_axil.clk) begin : auto_enable_logic
|
|
if (mgt_axil.rst) begin
|
|
auto_rst0 <= 1'b1;
|
|
auto_rst1 <= 1'b1;
|
|
auto_rst2 <= 1'b1;
|
|
auto_rst3 <= 1'b1;
|
|
auto_connect_state <= ST_RESET;
|
|
stat_auto_config_done_bclk <= 1'b0;
|
|
mgt_axil_in_progress <= 1'b0;
|
|
w_req <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
|
|
// default is to drive mgt_axi_through
|
|
/* write address channel */
|
|
auto_axil.awaddr <= 'bX;
|
|
auto_axil.awvalid <= 1'b0;
|
|
mgt_axil.awready <= 1'b0;
|
|
/* write data channel */
|
|
auto_axil.wdata <= 'bX;
|
|
auto_axil.wstrb <= 'b0;
|
|
auto_axil.wvalid <= 1'b0;
|
|
mgt_axil.wready <= 1'b0;
|
|
/* write resp channel */
|
|
mgt_axil.bresp[1:0] <= 'b0;
|
|
mgt_axil.bvalid <= 1'b0;
|
|
auto_axil.bready <= 1'b0;
|
|
/* read address channel */
|
|
auto_axil.araddr <= 'b0;
|
|
auto_axil.arvalid <= 1'b0;
|
|
mgt_axil.arready <= 1'b0;
|
|
/* read resp channel */
|
|
mgt_axil.rdata <= 'bX;
|
|
mgt_axil.rresp[1:0] <= 'b0;
|
|
mgt_axil.rvalid <= 1'b0;
|
|
auto_axil.rready <= 1'b0;
|
|
|
|
end else begin
|
|
// 4 clocks to mimic Xilinx Example behavior
|
|
auto_rst0 <= phy_reset_bclk;
|
|
auto_rst1 <= auto_rst0;
|
|
auto_rst2 <= auto_rst1;
|
|
auto_rst3 <= auto_rst2;
|
|
// assumes one access in flight at time (valid for standard Xilinx AXIL driver)
|
|
// set if anyone starts driving a W Address / W Data / R Address channel
|
|
if (auto_axil.awvalid || auto_axil.wvalid || auto_axil.arvalid) begin
|
|
mgt_axil_in_progress <= 1'b1;
|
|
// clear on an acknowledged response
|
|
end else if ((auto_axil.bvalid && auto_axil.bready) ||
|
|
(auto_axil.rvalid && auto_axil.rready)) begin
|
|
mgt_axil_in_progress <= 1'b0;
|
|
end
|
|
|
|
// default is to drive mgt_axi_through
|
|
/* write address channel */
|
|
auto_axil.awaddr <= mgt_axil.awaddr;
|
|
auto_axil.awvalid <= mgt_axil.awvalid;
|
|
mgt_axil.awready <= auto_axil.awready;
|
|
/* write data channel */
|
|
auto_axil.wdata <= mgt_axil.wdata;
|
|
auto_axil.wstrb <= mgt_axil.wstrb;
|
|
auto_axil.wvalid <= mgt_axil.wvalid;
|
|
mgt_axil.wready <= auto_axil.wready;
|
|
/* write resp channel */
|
|
mgt_axil.bresp <= auto_axil.bresp;
|
|
mgt_axil.bvalid <= auto_axil.bvalid;
|
|
auto_axil.bready <= mgt_axil.bready;
|
|
/* read address channel */
|
|
auto_axil.araddr <= mgt_axil.araddr;
|
|
auto_axil.arvalid <= mgt_axil.arvalid;
|
|
mgt_axil.arready <= auto_axil.arready;
|
|
/* read resp channel */
|
|
mgt_axil.rdata <= auto_axil.rdata;
|
|
mgt_axil.rresp <= auto_axil.rresp;
|
|
mgt_axil.rvalid <= auto_axil.rvalid;
|
|
auto_axil.rready <= mgt_axil.rready;
|
|
|
|
if (auto_rst3) begin
|
|
auto_connect_state = ST_RESET;
|
|
stat_auto_config_done_bclk <= 1'b0;
|
|
end else begin
|
|
case (auto_connect_state)
|
|
|
|
ST_RESET: begin
|
|
stat_auto_config_done_bclk <= 1'b0;
|
|
if (!mgt_axil_in_progress && auto_enable) begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_REG1_IDLE;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_REG1_IDLE: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// start transmitting alignment pattern
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_enable] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_idle] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_lfi] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_rfi] <= 1;
|
|
auto_axil.wdata[ctl_tx_ctl_test_pattern] <= 0;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// configure fec
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable_correction] <= 1;
|
|
auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable_indication] <= 1;
|
|
auto_axil.wdata[rs_fec_in_ctl_rsfec_ieee_error_indication_mode] <= 1;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= RSFEC_CONFIG_INDICATION_CORRECTION;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_RSFEC_CONFIG_ENABLE;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_RSFEC_CONFIG_ENABLE: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// enable fec
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable] <= 1;
|
|
auto_axil.wdata[rs_fec_in_ctl_tx_rsfec_enable] <= 1;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= RSFEC_CONFIG_ENABLE;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_RX_REG1;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_RX_REG1: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_rx_ctl_enable] <= 1;
|
|
auto_axil.wdata[ctl_rx_ctl_rx_force_resync] <= 0;
|
|
auto_axil.wdata[ctl_rx_ctl_test_pattern] <= 0;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_RX_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WAIT;
|
|
end
|
|
end
|
|
|
|
ST_WAIT: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// don't drive any writes, but hold off bus
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wstrb <= 0;
|
|
auto_axil.wvalid <= 0;
|
|
auto_axil.awaddr <= 0;
|
|
auto_axil.awvalid <= 0;
|
|
auto_axil.bready <= 0;
|
|
if (stat_rx_aligned_bclk) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// stop transmitting alignment pattern
|
|
// and start transmitting data
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_enable] <= 1;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_idle] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_lfi] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_tx_send_rfi] <= 0;
|
|
auto_axil.wdata[ctl_tx_ctl_test_pattern] <= 0;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
if (PAUSE_EN) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end else begin
|
|
auto_connect_state <= ST_READY;
|
|
end
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
//3DFF - 0011 1101 1111 1111
|
|
auto_axil.wdata[ctl_rx_pause_en+:9] <= '1;
|
|
auto_axil.wdata[ctl_rx_enable_gcp] <= 1;
|
|
auto_axil.wdata[ctl_rx_enable_pcp] <= 1;
|
|
auto_axil.wdata[ctl_rx_enable_gpp] <= 1;
|
|
auto_axil.wdata[ctl_rx_enable_ppp] <= 1;
|
|
//ctl_rx_pause_ack = 23; // 8 bits NOT SET
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
//1C631 - 0001 1100 0110 0011 0001
|
|
auto_axil.wdata[ctl_rx_check_mcast_gcp ] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_ucast_gcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_sa_gcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_etype_gcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_opcode_gcp] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_mcast_pcp ] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_ucast_pcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_sa_pcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_etype_pcp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_opcode_pcp] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_mcast_gpp ] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_ucast_gpp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_sa_gpp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_etype_gpp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_opcode_gpp] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_opcode_ppp] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_mcast_ppp ] <= 1; //1
|
|
auto_axil.wdata[ctl_rx_check_ucast_ppp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_sa_ppp ] <= 0;
|
|
auto_axil.wdata[ctl_rx_check_etype_ppp ] <= 0;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_quanta0+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wdata[ctl_tx_pause_quanta1+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_quanta2+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wdata[ctl_tx_pause_quanta3+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_quanta4+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wdata[ctl_tx_pause_quanta5+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_quanta6+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wdata[ctl_tx_pause_quanta7+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_quanta8+:16] <= PAUSE_QUANTA;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer0+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer1+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer2+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer3+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer4+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer5+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer6+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer7+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
auto_axil.wdata[ctl_tx_pause_refresh_timer8+:16] <= PAUSE_REFRESH;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1;
|
|
w_req <= 1'b1;
|
|
aw_req <= 1'b1;
|
|
end
|
|
end
|
|
|
|
ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1: begin
|
|
mgt_axil.awready <= 0;
|
|
mgt_axil.wready <= 0;
|
|
mgt_axil.arready <= 0;
|
|
auto_axil.arvalid <= 0;
|
|
// turn on RX interface
|
|
auto_axil.wdata <= 0;
|
|
// 1FF
|
|
auto_axil.wdata[ctl_tx_pause_enable+:9] <= '1;
|
|
auto_axil.wstrb <= '1;
|
|
auto_axil.wvalid <= w_req;
|
|
auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1;
|
|
auto_axil.awvalid <= aw_req;
|
|
auto_axil.bready <= 1'b1;
|
|
if (auto_axil.wready) begin
|
|
auto_axil.wvalid <= 1'b0;
|
|
w_req <= 1'b0;
|
|
end
|
|
if (auto_axil.awready) begin
|
|
auto_axil.awvalid <= 1'b0;
|
|
aw_req <= 1'b0;
|
|
end
|
|
if (auto_axil.bvalid) begin
|
|
auto_connect_state <= ST_READY;
|
|
end
|
|
end
|
|
|
|
ST_READY: begin
|
|
stat_auto_config_done_bclk <= 1'b1;
|
|
if (!stat_rx_aligned_bclk) begin
|
|
auto_connect_state <= ST_RESET;
|
|
end
|
|
end
|
|
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
always_comb begin
|
|
`AXI4LITE_ASSIGN(mgt_axil_v,auto_axil)
|
|
|
|
// window address to 0x0000-x1FFF
|
|
mgt_axil_v.araddr = 0;
|
|
mgt_axil_v.araddr[12:0] = auto_axil.araddr[12:0];
|
|
// window address to 0x0000-x1FFF
|
|
mgt_axil_v.awaddr = 0;
|
|
mgt_axil_v.awaddr[12:0] = auto_axil.awaddr[12:0];
|
|
end
|
|
|
|
end else begin : no_auto_connect
|
|
|
|
always_comb begin
|
|
`AXI4LITE_ASSIGN(mgt_axil_v,mgt_axil)
|
|
|
|
// window address to 0x0000-x1FFF
|
|
mgt_axil_v.araddr = 0;
|
|
mgt_axil_v.araddr[12:0] = mgt_axil.araddr[12:0];
|
|
// window address to 0x0000-x1FFF
|
|
mgt_axil_v.awaddr = 0;
|
|
mgt_axil_v.awaddr[12:0] = mgt_axil.awaddr[12:0];
|
|
|
|
stat_auto_config_done_bclk = 1'b1;
|
|
end
|
|
end
|
|
|
|
import PkgEth100gLbus::*;
|
|
|
|
|
|
lbus_t lbus_rx [3:0];
|
|
lbus_t lbus_tx [3:0];
|
|
logic lbus_tx_rdyout;
|
|
|
|
eth_100g_lbus2axi #(.NUM_SEG(4)) lbus2axi (
|
|
.axis(eth100g_rx),
|
|
.lbus_in(lbus_rx)
|
|
);
|
|
|
|
eth_100g_axi2lbus #(.NUM_SEG(4)) axi2lbus (
|
|
.axis(eth100g_tx),
|
|
.lbus_rdy(lbus_tx_rdyout),
|
|
.lbus_out(lbus_tx)
|
|
);
|
|
|
|
eth_100g_bd eth_100g_bd_i (
|
|
.refclk_clk_n(refclk_n),
|
|
.refclk_clk_p(refclk_p),
|
|
.gt_serial_port_0_grx_n(rx_n),
|
|
.gt_serial_port_0_grx_p(rx_p),
|
|
.gt_serial_port_0_gtx_n(tx_n),
|
|
.gt_serial_port_0_gtx_p(tx_p),
|
|
.init_clk(clk100),
|
|
.sys_reset(areset),
|
|
.usr_rx_reset(usr_rx_reset),
|
|
.usr_tx_reset(usr_tx_reset),
|
|
.gt_txusrclk2(mgt_clk),
|
|
.rx_clk(mgt_clk), //feedback in
|
|
.tx_ovfout(tx_ovfout),
|
|
.tx_unfout(tx_unfout),
|
|
.stat_rx_aligned(stat_rx_aligned),
|
|
.drp_clk(clk100),
|
|
.core_drp_daddr(10'b0),
|
|
.core_drp_den(1'b0),
|
|
.core_drp_di(16'b0),
|
|
.core_drp_do(),
|
|
.core_drp_drdy(),
|
|
.core_drp_dwe(1'b0),
|
|
`AXI4LITE_PORT_ASSIGN(s_axi,mgt_axil_v)
|
|
.pm_tick(pm_tick),
|
|
.ctl_tx_pause_req(ctl_tx_pause_req),
|
|
.ctl_tx_resend_pause(ctl_tx_resend_pause),
|
|
.stat_rx_pause_req(stat_rx_pause_req),
|
|
.eth100g_rx_lbus_seg0_data(lbus_rx[0].data),
|
|
.eth100g_rx_lbus_seg0_ena(lbus_rx[0].ena),
|
|
.eth100g_rx_lbus_seg0_eop(lbus_rx[0].eop),
|
|
.eth100g_rx_lbus_seg0_err(lbus_rx[0].err),
|
|
.eth100g_rx_lbus_seg0_mty(lbus_rx[0].mty),
|
|
.eth100g_rx_lbus_seg0_sop(lbus_rx[0].sop),
|
|
.eth100g_rx_lbus_seg1_data(lbus_rx[1].data),
|
|
.eth100g_rx_lbus_seg1_ena(lbus_rx[1].ena),
|
|
.eth100g_rx_lbus_seg1_eop(lbus_rx[1].eop),
|
|
.eth100g_rx_lbus_seg1_err(lbus_rx[1].err),
|
|
.eth100g_rx_lbus_seg1_mty(lbus_rx[1].mty),
|
|
.eth100g_rx_lbus_seg1_sop(lbus_rx[1].sop),
|
|
.eth100g_rx_lbus_seg2_data(lbus_rx[2].data),
|
|
.eth100g_rx_lbus_seg2_ena(lbus_rx[2].ena),
|
|
.eth100g_rx_lbus_seg2_eop(lbus_rx[2].eop),
|
|
.eth100g_rx_lbus_seg2_err(lbus_rx[2].err),
|
|
.eth100g_rx_lbus_seg2_mty(lbus_rx[2].mty),
|
|
.eth100g_rx_lbus_seg2_sop(lbus_rx[2].sop),
|
|
.eth100g_rx_lbus_seg3_data(lbus_rx[3].data),
|
|
.eth100g_rx_lbus_seg3_ena(lbus_rx[3].ena),
|
|
.eth100g_rx_lbus_seg3_eop(lbus_rx[3].eop),
|
|
.eth100g_rx_lbus_seg3_err(lbus_rx[3].err),
|
|
.eth100g_rx_lbus_seg3_mty(lbus_rx[3].mty),
|
|
.eth100g_rx_lbus_seg3_sop(lbus_rx[3].sop),
|
|
.eth100g_tx_lbus_seg0_data(lbus_tx[0].data),
|
|
.eth100g_tx_lbus_seg0_ena(lbus_tx[0].ena),
|
|
.eth100g_tx_lbus_seg0_eop(lbus_tx[0].eop),
|
|
.eth100g_tx_lbus_seg0_err(lbus_tx[0].err),
|
|
.eth100g_tx_lbus_seg0_mty(lbus_tx[0].mty),
|
|
.eth100g_tx_lbus_seg0_sop(lbus_tx[0].sop),
|
|
.eth100g_tx_lbus_seg1_data(lbus_tx[1].data),
|
|
.eth100g_tx_lbus_seg1_ena(lbus_tx[1].ena),
|
|
.eth100g_tx_lbus_seg1_eop(lbus_tx[1].eop),
|
|
.eth100g_tx_lbus_seg1_err(lbus_tx[1].err),
|
|
.eth100g_tx_lbus_seg1_mty(lbus_tx[1].mty),
|
|
.eth100g_tx_lbus_seg1_sop(lbus_tx[1].sop),
|
|
.eth100g_tx_lbus_seg2_data(lbus_tx[2].data),
|
|
.eth100g_tx_lbus_seg2_ena(lbus_tx[2].ena),
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.eth100g_tx_lbus_seg2_eop(lbus_tx[2].eop),
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.eth100g_tx_lbus_seg2_err(lbus_tx[2].err),
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.eth100g_tx_lbus_seg2_mty(lbus_tx[2].mty),
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.eth100g_tx_lbus_seg2_sop(lbus_tx[2].sop),
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.eth100g_tx_lbus_seg3_data(lbus_tx[3].data),
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.eth100g_tx_lbus_seg3_ena(lbus_tx[3].ena),
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.eth100g_tx_lbus_seg3_eop(lbus_tx[3].eop),
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.eth100g_tx_lbus_seg3_err(lbus_tx[3].err),
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.eth100g_tx_lbus_seg3_mty(lbus_tx[3].mty),
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.eth100g_tx_lbus_seg3_sop(lbus_tx[3].sop),
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.eth100g_tx_tx_rdyout(lbus_tx_rdyout));
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endmodule
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