Wade Fife
dce6ce8063
This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
12 lines
278 B
Makefile
12 lines
278 B
Makefile
#
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RFNOC_BLOCK_DDC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_ddc/, \
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noc_shell_ddc.v \
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rfnoc_block_ddc_regs.vh \
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rfnoc_block_ddc.v \
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))
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