miegl
90e0b1d038
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim. Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
// SPDX-License-Identifier: LGPL-3.0-or-later
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// Drop-in replacement for Ettus/X300 fifo_short_2clk FIFO Generator IP.
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// X300 configuration: 72 bits x 32 words, independent clocks,
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// distributed RAM, FWFT, 3 CDC synchronization stages.
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`timescale 1ns/1ps
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`default_nettype none
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module fifo_short_2clk (
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input wire rst,
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input wire wr_clk,
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input wire [71:0] din,
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input wire wr_en,
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output wire full,
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output wire [5:0] wr_data_count,
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input wire rd_clk,
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output wire [71:0] dout,
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input wire rd_en,
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output wire empty,
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output wire [5:0] rd_data_count
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);
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fifo_2clk_xpm_core #(
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.FIFO_DEPTH (32),
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.COUNT_WIDTH (6),
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.CDC_SYNC_STAGES (3),
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.MEMORY_TYPE ("distributed")
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) impl_i (
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.rst (rst),
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.wr_clk (wr_clk),
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.din (din),
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.wr_en (wr_en),
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.full (full),
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.wr_data_count(wr_data_count),
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.rd_clk (rd_clk),
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.dout (dout),
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.rd_en (rd_en),
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.empty (empty),
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.rd_data_count(rd_data_count)
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);
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endmodule
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`default_nettype wire
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