miegl
eb84b6c949
Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths. This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.
213 lines
7.6 KiB
Verilog
213 lines
7.6 KiB
Verilog
// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Vivado/XPM replacement for the legacy Ettus FIFO Generator building blocks
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// used by axi_fifo_2clk.v on Xilinx 7-series devices.
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//
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// This core deliberately provides the old native FIFO interface while using
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// xpm_fifo_async internally. The external reset may be asynchronous, as it
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// was for the FIFO Generator instances. XPM's rst input, however, must be
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// synchronous to wr_clk, so reset assertion is captured asynchronously and
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// then presented to XPM through a wr_clk synchronizer. Read/write requests
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// and external flags are held inactive/conservative until XPM reset-busy has
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// cleared.
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`timescale 1ns/1ps
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`default_nettype none
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module fifo_2clk_xpm_core #(
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parameter integer FIFO_DEPTH = 32,
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parameter integer COUNT_WIDTH = 6,
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parameter integer CDC_SYNC_STAGES = 3,
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parameter MEMORY_TYPE = "distributed"
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)(
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input wire rst,
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input wire wr_clk,
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input wire [71:0] din,
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input wire wr_en,
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output wire full,
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output wire [COUNT_WIDTH-1:0] wr_data_count,
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input wire rd_clk,
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output wire [71:0] dout,
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input wire rd_en,
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output wire empty,
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output wire [COUNT_WIDTH-1:0] rd_data_count
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);
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// ------------------------------------------------------------------------
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// Reset adaptation
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// ------------------------------------------------------------------------
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// Legacy FIFO Generator accepted an asynchronous reset. XPM_FIFO_ASYNC
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// requires rst to be synchronous to wr_clk. rst_capture catches even a
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// short asynchronous assertion; xpm_rst_sync then converts it into a reset
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// signal that changes only on wr_clk edges.
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reg rst_capture = 1'b1;
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always @(posedge wr_clk or posedge rst) begin
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if (rst)
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rst_capture <= 1'b1;
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else
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rst_capture <= 1'b0;
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end
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(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
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reg [1:0] xpm_rst_sync = 2'b11;
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always @(posedge wr_clk) begin
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xpm_rst_sync[0] <= rst_capture;
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xpm_rst_sync[1] <= xpm_rst_sync[0];
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end
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wire xpm_rst = xpm_rst_sync[1];
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wire xpm_full;
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wire xpm_empty;
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wire xpm_wr_rst_busy;
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wire xpm_rd_rst_busy;
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wire [71:0] xpm_dout;
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wire [COUNT_WIDTH-1:0] xpm_wr_data_count;
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wire [COUNT_WIDTH-1:0] xpm_rd_data_count;
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// ------------------------------------------------------------------------
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// Read-domain reset/hold handling
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// ------------------------------------------------------------------------
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// Do NOT combine xpm_rst (wr_clk domain) with rd-domain signals and feed the
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// result into an asynchronous PRE/CLR. Vivado report_cdc correctly reports
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// that topology as CDC-10 (combinational logic before a synchronizer).
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//
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// Instead, synchronize each reset indication into rd_clk using dedicated XPM
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// CDC structures, then make all hold/release decisions synchronously in the
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// read domain.
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// Preserve the legacy FIFO Generator behavior at the external interface:
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// assertion of rst is visible immediately in the read domain, while release
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// is synchronized to rd_clk.
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wire legacy_rd_rst;
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xpm_cdc_async_rst #(
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.DEST_SYNC_FF (2),
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.INIT_SYNC_FF (1),
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.RST_ACTIVE_HIGH(1)
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) legacy_rd_rst_sync_i (
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.src_arst (rst),
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.dest_clk (rd_clk),
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.dest_arst(legacy_rd_rst)
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);
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// xpm_rst is generated synchronously in the write domain. Synchronize that
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// reset request into rd_clk so the read interface can remain held until the
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// XPM reset has actually propagated through the write side. INIT=1 keeps the
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// read side conservative during FPGA configuration/startup.
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wire xpm_rst_rd;
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xpm_cdc_sync_rst #(
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.DEST_SYNC_FF (2),
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.INIT (1),
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.INIT_SYNC_FF (1),
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.SIM_ASSERT_CHK(1)
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) xpm_rst_to_rd_i (
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.src_rst (xpm_rst),
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.dest_clk(rd_clk),
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.dest_rst(xpm_rst_rd)
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);
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// A reset event is complete only after the read domain has observed the XPM
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// reset sequence (xpm_rst_rd and/or rd_rst_busy asserted) and both indicators
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// have subsequently gone low. This prevents a short external reset from
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// creating a gap where the legacy interface is released before XPM has
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// propagated the reset from wr_clk into rd_clk.
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reg rd_reset_pending = 1'b1;
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reg rd_reset_seen = 1'b0;
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reg legacy_rd_rst_d = 1'b1;
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always @(posedge rd_clk) begin
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legacy_rd_rst_d <= legacy_rd_rst;
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// Start a fresh acknowledgement cycle for each external reset event.
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if (legacy_rd_rst && !legacy_rd_rst_d) begin
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rd_reset_pending <= 1'b1;
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rd_reset_seen <= 1'b0;
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end else if (legacy_rd_rst) begin
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// The XPM reset may assert and even complete while the legacy reset is
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// still being synchronously released. Remember that it was observed.
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rd_reset_pending <= 1'b1;
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if (xpm_rst_rd || xpm_rd_rst_busy)
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rd_reset_seen <= 1'b1;
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end else if (rd_reset_pending) begin
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if (xpm_rst_rd || xpm_rd_rst_busy)
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rd_reset_seen <= 1'b1;
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if (rd_reset_seen && !xpm_rst_rd && !xpm_rd_rst_busy)
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rd_reset_pending <= 1'b0;
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end
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end
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// All terms below are now local to rd_clk (or an XPM-synchronized reset).
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wire rd_hold = legacy_rd_rst | rd_reset_pending |
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xpm_rst_rd | xpm_rd_rst_busy;
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wire wr_hold = rst | xpm_rst | xpm_wr_rst_busy;
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// XPM requires wr_en/rd_en low while reset or the corresponding reset-busy
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// flag is active. Gating with full/empty also suppresses overflow/underflow
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// requests from legacy call sites that leave an enable asserted continuously.
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wire xpm_wr_en = wr_en & ~wr_hold & ~xpm_full;
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wire xpm_rd_en = rd_en & ~rd_hold & ~xpm_empty;
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// Match the conservative reset behavior of the Ettus FIFO Generator IP:
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// full is asserted during reset and empty is asserted until read-side reset
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// recovery is complete.
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assign full = wr_hold | xpm_full;
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assign empty = rd_hold | xpm_empty;
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assign dout = rd_hold ? 72'b0 : xpm_dout;
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assign wr_data_count = wr_hold ? {COUNT_WIDTH{1'b0}} : xpm_wr_data_count;
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assign rd_data_count = rd_hold ? {COUNT_WIDTH{1'b0}} : xpm_rd_data_count;
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// USE_ADV_FEATURES="0404" enables only wr_data_count (bit 2) and
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// rd_data_count (bit 10), preserving the legacy ports without enabling the
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// other optional status logic.
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xpm_fifo_async #(
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.CDC_SYNC_STAGES (CDC_SYNC_STAGES),
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.DOUT_RESET_VALUE ("0"),
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.ECC_MODE ("no_ecc"),
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.FIFO_MEMORY_TYPE (MEMORY_TYPE),
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.FIFO_READ_LATENCY (0),
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.FIFO_WRITE_DEPTH (FIFO_DEPTH),
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.FULL_RESET_VALUE (1),
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.PROG_EMPTY_THRESH (10),
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.PROG_FULL_THRESH (10),
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.RD_DATA_COUNT_WIDTH(COUNT_WIDTH),
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.READ_DATA_WIDTH (72),
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.READ_MODE ("fwft"),
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.RELATED_CLOCKS (0),
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.SIM_ASSERT_CHK (1),
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.USE_ADV_FEATURES ("0404"),
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.WAKEUP_TIME (0),
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.WRITE_DATA_WIDTH (72),
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.WR_DATA_COUNT_WIDTH(COUNT_WIDTH)
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) xpm_fifo_async_i (
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.almost_empty (),
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.almost_full (),
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.data_valid (),
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.dbiterr (),
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.dout (xpm_dout),
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.empty (xpm_empty),
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.full (xpm_full),
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.overflow (),
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.prog_empty (),
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.prog_full (),
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.rd_data_count(xpm_rd_data_count),
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.rd_rst_busy (xpm_rd_rst_busy),
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.sbiterr (),
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.underflow (),
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.wr_ack (),
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.wr_data_count(xpm_wr_data_count),
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.wr_rst_busy (xpm_wr_rst_busy),
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.din (din),
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.injectdbiterr(1'b0),
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.injectsbiterr(1'b0),
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.rd_clk (rd_clk),
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.rd_en (xpm_rd_en),
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.rst (xpm_rst),
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.sleep (1'b0),
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.wr_clk (wr_clk),
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.wr_en (xpm_wr_en)
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);
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endmodule
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`default_nettype wire
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