Wade Fife b4943f4a61 fpga: tools: Disable common simulation warnings ...

This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.


Original-commit: f094aa7ae0f864764276c5c67c51b21547327fb0

2025-03-17 13:40:26 -05:00

..

make

fpga: tools: Add support for Questa

2025-03-17 13:40:26 -05:00

scripts

fpga: tools: Disable common simulation warnings

2025-03-17 13:40:26 -05:00

utils

fpga: tools: Fix issues in run_testbenches.py

2025-03-14 08:03:34 +01:00