48 lines
1.4 KiB
Systemverilog
48 lines
1.4 KiB
Systemverilog
//
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// Copyright 2024 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Package: ctrlport_pkg
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//
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// Description:
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//
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// Defines constants for the control-port interface.
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//
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package ctrlport_pkg;
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`include "ctrlport.vh"
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// typedef for status
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typedef enum logic [1:0] {
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STS_OKAY = CTRL_STS_OKAY,
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STS_CMDERR = CTRL_STS_CMDERR,
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STS_TSERR = CTRL_STS_TSERR,
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STS_WARNING = CTRL_STS_WARNING } ctrlport_status_t;
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// Defining signals as defined in Table 18 of RFNoC Specification v.1.0.1.
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// request related signals
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typedef struct packed {
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logic wr;
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logic rd;
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logic [ CTRLPORT_ADDR_W-1:0] addr;
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logic [ CTRLPORT_PORTID_W-1:0] port_id;
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logic [CTRLPORT_REM_EPID_W-1:0] remote_epid;
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logic [ CTRLPORT_PORTID_W-1:0] remote_portid;
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logic [ CTRLPORT_DATA_W-1:0] data;
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logic [ CTRLPORT_BYTE_EN_W-1:0] byte_en;
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logic has_time;
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// signal time - renamed to timestamp to avoid conflict with SystemVerilog keyword time
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logic [ CTRLPORT_TIME_W-1:0] timestamp;
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} ctrlport_request_t;
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// response related signals
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typedef struct packed {
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logic ack;
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ctrlport_status_t status;
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logic [CTRLPORT_DATA_W-1:0] data;
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} ctrlport_response_t;
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endpackage : ctrlport_pkg
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