75 lines
2.1 KiB
Makefile
75 lines
2.1 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir.
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BASE_DIR = ../../../../..
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(WISHBONE_SRCS) \
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)
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DESIGN_SRCS += $(abspath \
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../../regmap/fbx_ctrl_regmap_utils.vh \
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../../regmap/clock_en_regmap_utils.vh \
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../../clock_en_control.v \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = $(BASE_DIR)/x400/ip
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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#
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# These TBs don't use any IP yet :)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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include $(BASE_DIR)/../sim/general/Makefile.srcs
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# Define only one top-level module
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SIM_TOP = clock_en_control_tb glbl
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# Simulation runtime in microseconds
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SIM_RUNTIME_US = 100000
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SIM_SRCS = \
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$(abspath clock_en_control_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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