Andrew Moch
8cb9bdd331
Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros. Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
31 lines
970 B
Systemverilog
31 lines
970 B
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Package: PkgAxi
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// Description:
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// AXI4 is an ARM standard for memory mapped burst transfers
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// For more information on the spec see
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// - https://developer.arm.com/docs/ihi0022/d
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//
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// This package contains types used for AxiIf.
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//
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//-----------------------------------------------------------------------------
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// AXI4 Package
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//-----------------------------------------------------------------------------
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package PkgAxi;
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typedef enum logic [1:0] {OKAY=0,SLVERR=2,DECERR=3} axi_resp_t;
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// Len - Burst Length = LEN+1
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// Size - Bytes in transfer = 2**SIZE
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typedef enum logic [1:0] {FIXED=0,INCR=1,WRAP=2} axi_burst_t;
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// Cache - just see the docs. (too tangled!)
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// Prot[0] - Privleged
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// Prot[1] - Secure
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// Prot[2] - 0=Data / 1=Instruction
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// QOS - 0 = no protocol - Others not specified in spec
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endpackage : PkgAxi
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