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Martin Braun 4d4b06dfac fpga: Cosmetic changes to rx_frontend_gen3_tb 
- Add different signal types
- Default to real/constant
- Minor cleanup


Original-commit: 0624d6c6452fa47c47bb33abc1eb8ef935cfcf1f
2022-12-02 11:42:44 -08:00
..
blocks
fpga: Cosmetic changes to rx_frontend_gen3_tb
2022-12-02 11:42:44 -08:00
core
fpga: rfnoc: Add CHDR management util functions
2021-11-04 11:04:54 -05:00
crossbar
fpga: rfnoc: Add labels to axi_switch generate blocks
2021-10-28 23:15:41 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
fpga: lib: Add eth_ipv4_interface_tb
2022-08-29 17:01:45 -05:00
utils
fpga: rfnoc: Fix inferred latch in chdr_strip_header
2022-11-13 16:47:57 -06:00
xport
fpga: lib: Add MTU parameter to eth_internal
2022-09-01 14:41:55 -05:00
xport_sv
fpga: lib: Add verilog-compatible wrapper for eth_ipv4_interface
2022-08-29 17:01:45 -05:00
.gitignore
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
addsub.v
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2020-01-28 09:35:36 -08:00
addsub.vhd
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2020-01-28 09:35:36 -08:00
axi_async_stream.v
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axi_bit_reduce.v
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axi_clip_complex.v
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axi_clip_unsigned.v
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2020-01-28 09:35:36 -08:00
axi_clip.v
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2020-01-28 09:35:36 -08:00
axi_deserializer.v
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2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_fir_filter_dec.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter.v
fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
2022-02-10 18:11:41 -07:00
axi_join.v
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axi_packer.v
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axi_pipe_join.v
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axi_pipe_mac.v
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axi_pipe.v
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2020-01-28 09:35:36 -08:00
axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_repeat.v
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2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v
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axi_round_and_clip.v
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axi_round_complex.v
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axi_round.v
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2020-01-28 09:35:36 -08:00
axi_serializer.v
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2020-01-28 09:35:36 -08:00
axi_sync.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
axi_tag_time.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
cadd.v
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chdr_fifo_large.v
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cic_decimate.v
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cic_interpolate.v
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cmul.v
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complex_invert.v
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complex_to_mag_approx.v
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complex_to_magsq.v
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conj.v
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const_sreg.v
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const.v
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counter.v
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2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v
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cvita_hdr_encoder.v
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cvita_hdr_modify.v
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cvita_hdr_parser.v
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data_types.vh
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datapath_gatekeeper.v
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ddc.v
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2020-01-28 09:35:36 -08:00
dds_freq_tune_duc.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
dds_freq_tune.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
dds_timed.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
dds_wrapper.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
delay_fifo.v
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delay_type2.v
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delay_type3.v
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delay_type4.v
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duc.v
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fft_shift.v
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file_sink.v
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2020-01-28 09:35:36 -08:00
file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
join_complex.v
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keep_one_in_n.v
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2020-01-28 09:35:36 -08:00
Makefile.srcs
fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh
2022-01-25 14:09:15 -07:00
moving_sum.v
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mult_add_rc.v
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mult_add.v
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mult_rc.v
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mult.v
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multiply.v
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noc_traffic_counter.v
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null_source.v
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periodic_framer.v
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phase_accum.v
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ram_to_fifo.v
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2020-01-28 09:35:36 -08:00
sine_tone.v
siggen: Fix direction of rotation
2021-10-27 07:56:09 -07:00
split_complex.v
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2020-01-28 09:35:36 -08:00
split_stream_fifo.v
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split_stream.v
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2020-01-28 09:35:36 -08:00
vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00