61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
416 lines
21 KiB
Tcl
416 lines
21 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Common timing constraints for X410.
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#
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###############################################################################
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# Motherboard Clocks
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###############################################################################
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# 10/25 MHz reference clock from rear panel connector.
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# Constrain to the fastest possible clock rate.
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set ref_clk_period 40.00
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create_clock -name ref_clk -period $ref_clk_period [get_ports BASE_REFCLK_FPGA_P]
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# PLL Reference Clock. Used to derive data clocks.
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# Constrain to the fastest possible clock rate supported in the driver.
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# MPM supports 61.44 / 62.5 / 64.0 MHz.
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set pll_ref_clk_period 15.625
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create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
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# MGT Clocks
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# Clock Reference | Frequency | Purpose
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# MGT_REFCLK_LMK0 | 156.25/125 MHz | 10 GbE
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# MGT_REFCLK_LMK1 | 100.00 MHz | Reserved
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# MGT_REFCLK_LMK2 | 100.00 MHz | Reserved
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# MGT_REFCLK_LMK3 | 156.25/125 MHz | 10 GbE
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create_clock -name mgt_ref_0 -period 6.400 [get_ports MGT_REFCLK_LMK0_P]
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create_clock -name mgt_ref_1 -period 10.000 [get_ports MGT_REFCLK_LMK1_P]
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create_clock -name mgt_ref_2 -period 10.400 [get_ports MGT_REFCLK_LMK2_P]
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create_clock -name mgt_ref_3 -period 6.400 [get_ports MGT_REFCLK_LMK3_P]
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# Virtual clocks for constraining misc. I/Os.
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create_clock -name async_in_clk -period 50.00
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create_clock -name async_out_clk -period 50.00
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###############################################################################
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# Aliases for auto-generated clocks
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###############################################################################
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# Name the PS clocks. These are originally declared in the PS8 IP block.
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# Create the clocks based on the PS PLCLK pins.
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# This generates critical warnings in the OSS flow because the clocks were already
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# define and we are completely rewriting the old clock definition... this is OK.
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create_clock -name clk100 -period 10.000 \
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[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[0]}]
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create_clock -name clk40 -period 25.000 \
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[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[1]}]
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create_clock -name clk166 -period 6.000 \
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[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[2]}]
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create_clock -name clk200 -period 5.000 \
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[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[3]}]
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###############################################################################
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# Sync to DB synthesizer sync CPLD input
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###############################################################################
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# synth_sync_hold_requirement and synth_sync_setup_requirement are shared
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# between the FPGA and DB CPLD. The values are set in shared_constants.sdc
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set synth_sync_ports [get_ports {DB0_SYNTH_SYNC DB1_SYNTH_SYNC}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min -$synth_sync_hold_requirement $synth_sync_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $synth_sync_setup_requirement $synth_sync_ports
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###############################################################################
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# SPI to MB CPLD (PL)
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# This interface is defined as system synchronous to pll_ref_clk.
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###############################################################################
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# The output delays are chosen to allow a large time window of valid data for
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# the MB CPLD logic.
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set spi_min_out_delay 0.000
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set spi_max_out_delay 11.000
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# Set output constraints for all ports.
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set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
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# Both CPLD and FPGA use PLL reference clock from a common clock chip.
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# The traces from that clock chip to the ICs are not length matched. Assume a
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# worst case clock difference of 0.5 ns at the IC inputs. There is no direction
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# defined. The clock can arrive faster or slower at one IC.
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set pl_clock_diff 0.500
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# The longest trace on the PL SPI interface is (assuming 170.0 ps/in)
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# Longest trace | Trace length | Trace delay
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# PL_CPLD_MISO | 3.863 in | 0.657 ns
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set pl_spi_board_delay 0.657
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# Output delay timings of the MB CPLD design, which still meet timing
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set pl_spi_cpld_min_out -1.000
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set pl_spi_cpld_max_out 8.000
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set spi_in_port [get_ports {PL_CPLD_MISO}]
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set_input_delay -clock [get_clocks pll_ref_clk] \
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-min [expr {- $pl_spi_cpld_min_out - $pl_clock_diff}] \
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$spi_in_port
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set_input_delay -clock [get_clocks pll_ref_clk] \
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-max [expr {$pll_ref_clk_period - $pl_spi_cpld_max_out + $pl_spi_board_delay + $pl_clock_diff}] \
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$spi_in_port
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###############################################################################
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# 10 GbE
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###############################################################################
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# These are the exceptions from "xge_pcs_pma_exceptions.xdc" which are to be
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# used when not using the example design.
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#
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# "clk100" used here is the clock that's connected to the "dclk" input in the core.
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set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
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set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
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set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk100] -datapath_only 6.40
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set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk100] -datapath_only 6.40
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set_max_delay -from [get_clocks clk100] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
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set_max_delay -from [get_clocks clk100] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
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###############################################################################
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# DIO
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# Those GPIO pins are considered asynchronous paths. The user has to add
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# constraints in case required. Therefore not setting false_paths from / to
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# user logic to allow user generated timing constraints to be applied.
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###############################################################################
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# Ignore paths from "slow" PS interface to not interfere with user constraints.
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set dio_ports [get_ports {DIOA_FPGA[*] DIOB_FPGA[*]}]
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set dio_registers [get_cells -hierarchical -filter {NAME =~ *x4xx_dio_i* && IS_SEQUENTIAL && IS_PRIMITIVE}]
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set_false_path -from $dio_registers -to $dio_ports
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set_false_path -from $dio_ports -to $dio_registers
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###############################################################################
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# PPS
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###############################################################################
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# The TRIG_IO port may be driven by either the PPS in BRC domain to
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# enable direct sync between 2 devices, or by any other user logic.
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# When PPS is exported through Trigger I/O, timing must be analyzed
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# to ensure determinism in the PPS exporting.
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# But, when other user logic drives TRIG_IO, then the port should be
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# treated as asynchronous (or close to async. at least).
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# To achieve this conditional timing analysis, the following trick is
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# used:
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# 1. A virtual copy of ref_clk is created for I/O timing - virtual_ref_clk
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# 2. Set output_delay constraints to assign a clock to the TRIG_IO port.
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# 3. A set_max_delay constraint is used to time the output path to TRIG_IO
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# set_max_delay makes the timing constraint driver agnostic, and as long
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# as the critical output delay is met for driving PPS through TRIG_IO,
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# we should be fine as this requirement is relatively loose.
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# 1) Creating copy of ref_clk to only analyze timing to TRIG_IO port (output)
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# when output is driven by ref_clk (PPS generation in ref_clk domain).
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create_clock -name virtual_ref_clk -period $ref_clk_period
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# Trigger IO port is used as output for the PPS signal
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# TRIG_IO_1V8 trace length MB = 4.050 + 1.190 inch = 5.240 inch
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# TRIG_IO_1V8 trace length DB = 2.401 + 0.120 + 0.457 + 0.261 inch = 3.239 inch
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# TRIG_IO buffer max switching time = 3.3
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set trig_max_out_delay [expr {8.479 * 0.17 + 3.3}]
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# Set minimum output delay hold time to a small amount to grant external
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# devices some hold time. Delay should be simple to achieve as there is no PLL
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# in the clocking path and some combinatorial logic.
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set trig_min_out_delay 2.000
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# 2) set_output_delay for assigning clocks to TRIG_IO. Use zero for delay to
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# avoid adding extra delay requirements on top of the set_max|min_delay
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# constraints below.
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set_output_delay -clock [get_clocks virtual_ref_clk] 0.0 [get_ports {TRIG_IO}]
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# 3) Min and max delays make constraining driver agnostic. We just make sure
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# the critical timing for PPS export is met though.
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set_max_delay -through [get_port {TRIG_IO}] -to [get_clocks {virtual_ref_clk}] \
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[expr {$ref_clk_period - $trig_max_out_delay}]
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set_min_delay -through [get_port {TRIG_IO}] -to [get_clocks {virtual_ref_clk}] \
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$trig_min_out_delay
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# Treat TRIG_IO input as asynchronous.
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set_false_path -from [get_ports {TRIG_IO}]
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# For documentation purposes, these are the input max/min delays for TRIG_IO:
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# - Input delay assuming zero trace delay and TRIG_IO buffer min switching
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# time (B->A) = 0.1 ns.
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# - TRIG_IO buffer max switching time (B->A = input) = 3.7 ns + same trace
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# length as for output (8.479).
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# Assuming no delay on external clock distribution.
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# Account for the PPS min output delay only (for the case two X410 are directly
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# connected to each other).
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set pps_min_in_delay $trig_min_out_delay
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# PPS_IN trace length DB = 0.535 + 0.133 + 0.117 + 0.061 + 2.745 inch = 3.591 inch
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# PPS_IN trace length MB = 5.726 inch
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# PPS switch max propagation delay = 3.6
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# Assume 50% of the clock period is used for external PPS clock distribution as
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# the PPS out is used to synchronize one X410 (master) with another X410
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# (slave) the PPS out (trig_io) delay is added to the PPS input.
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set pps_max_in_delay [expr {9.317 * 0.17 + 3.6 + 0.5 * $ref_clk_period + $trig_max_out_delay}]
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# Apply PPS input constraints.
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set_input_delay -clock [get_clocks ref_clk] -min $pps_min_in_delay [get_ports {PPS_IN}]
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set_input_delay -clock [get_clocks ref_clk] -max $pps_max_in_delay [get_ports {PPS_IN}]
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# PPS clock domain crossing BRC -> PRC on the aligned edge.
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# Use a data path of half PLL reference clock period to make sure the value is
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# captured without metastability.
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set_max_delay -from [get_cells -hierarchical pps_delayed_brc_reg] \
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-to [get_clocks pll_ref_clk*] [expr {$pll_ref_clk_period/2}]
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###############################################################################
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# LMK sync
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###############################################################################
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# The timings are derived from simulation.
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# Clock Buffer ADCLK944 -> FPGA.
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set buffer_to_fpga_min_clk_delay 0.997
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set buffer_to_fpga_max_clk_delay 1.154
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# Clock Buffer ADCLK944 -> Sample clock PLL (LMK04832).
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set buffer_to_spll_min_clk_delay 0.000
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set buffer_to_spll_max_clk_delay 0.014
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# FPGA -> Sample clock PLL SYNC input.
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set fpga_to_spll_min_clk_delay 0.381
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set fpga_to_spll_max_clk_delay 0.460
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# Sample clock PLL requirements.
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set lmk_sync_input_hold 4.000
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set lmk_sync_input_setup 4.000
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set lmk_sync_output_max_delay [expr {$fpga_to_spll_max_clk_delay + $buffer_to_fpga_max_clk_delay + \
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$lmk_sync_input_setup - $buffer_to_spll_min_clk_delay}]
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set lmk_sync_output_min_delay [expr {$fpga_to_spll_min_clk_delay + $buffer_to_fpga_min_clk_delay - \
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$buffer_to_spll_max_clk_delay - $lmk_sync_input_hold}]
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set_output_delay -clock ref_clk -max $lmk_sync_output_max_delay [get_ports {LMK_SYNC}]
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set_output_delay -clock ref_clk -min $lmk_sync_output_min_delay [get_ports {LMK_SYNC}]
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###############################################################################
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# SPLL SYSREF Capture
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###############################################################################
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# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
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# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
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# SYSREF and PLL reference clock are directly fed into the RFSoC.
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# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
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# output) with a double synchronizer and then transfered to the RFDC clock
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# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
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# sync. purposes.
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# SYSREF is a continuous signal running at PRC freq. / 25, and it is
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# intentionally shifted in the LMK chip to align it closer to the
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# PRC's falling edge.
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# The added delay follows the formula:
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# SYSREF LMK delay = 22 * sample clock period
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# The highest sampling frequency supported in MPM (3.072 GHz) is used for
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# timing constrains. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
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set sysref_lmk_delay 7.161
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#
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# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
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# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
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# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
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#
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# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
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# which essentially over-constrains SYSREF.
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#
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# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
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# calculated as follows:
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# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
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# - PRC prop. delay (min)
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set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
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#
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# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
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# is calculated as follows:
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# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
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# - PRC prop. delay (min)
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set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
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set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
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set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
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###############################################################################
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# DB GPIO
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# This interface is defined as system synchronous to pll_ref_clk.
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# Some timing constants in this section are declared in
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# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
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###############################################################################
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# Set output constraints for all ports.
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set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
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# Output enable signal is available one clock cycle ahead of valid data, this
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# enables the use of multi-cycle paths.
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set db_gpio_out_en_regs [get_cells -hierarchical -filter \
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{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
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set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
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set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
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# Calculate output delays back from capturing edge, add board delay and clock
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# difference.
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# Assume worst case as data being generated late and receiving an early clock:
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# - Max CPLD TCO
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# - Max data propagation delay
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# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
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# - Maximum delay from MC100EPT23 clock buffer
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set_input_delay -clock pll_ref_clk \
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-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
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+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
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$db_gpio_ports
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# Negate minimum output delay as it is defined from the change to the start
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# clock edge.
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# Assume worst case as data being generated early and receiving an late clock:
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# - Min CPLD TCO
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# - Min data propagation delay (0)
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# - Min CPLD clock propagation delay and max FPGA clock propagation delay
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set_input_delay -clock pll_ref_clk \
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-min [expr {- $db_gpio_cpld_min_out \
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- $db_gpio_board_min_delay \
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- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
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$db_gpio_ports
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###############################################################################
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# x4xx_ps_rfdc_bd
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###############################################################################
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# The calibration_muxes component contains a clock crossing from some GPIO
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# component instances that are synchronous to a configuration clock and ending
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# in some AXI registers synchronous to data clock. The GPIO registers are
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# essentially constant. When they are changing (due to a register write), the
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# latching registers can definitely become metastable, so the software must
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# ensure that the corrupted data appears at a safe time.
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set gpio_regs [get_pins -of [get_cells -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/axi_gpio*} -hier] -filter {IS_CLOCK}]
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set mux_regs [get_cells -hier -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/gpio_to_axis_mux*}]
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set_false_path -from $gpio_regs -to $mux_regs
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# This property tells Vivado that we require these clocks to be well aligned.
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# We have synchronous clock domain crossings between these clocks that can have
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# large hold violations after placement due to uneven clock loading.
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set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
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}]
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# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
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# code clocked in this domain will be reset after this clocked is enabled. This
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# will make timing easier to meet on these clock domains.
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
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|
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
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|
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
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|
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
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|
|
|
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###############################################################################
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# Misc Constraints
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###############################################################################
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|
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# Double synchronizer false paths.
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set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
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|
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */rf_reset_controller*/*_ms_reg/D}]
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|
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_nco_reset_0/*_ms*/D}]
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|
|
|
# GTY_RCV_CLK_* is driven by a OBUFDS_GTE4 buffer, which has an asynchronous
|
|
# clock-enable pin.
|
|
# By experimentation, it was observed that explicitly setting a false_path to
|
|
# this pin improved timing.
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|
set gty_rcv_clk_buff_ceb [get_pins -of_objects [get_cells -of_objects [all_fanin -flat -startpoints_only [get_ports {GTY_RCV_CLK_P}]]] -filter {NAME=~ "*CEB"}]
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|
set_false_path -from [get_clocks {clk40}] -through $gty_rcv_clk_buff_ceb
|
|
|
|
|
|
###############################################################################
|
|
# Asynchronous / misc. I/O constraints
|
|
# Loosely constrain these to prevent warnings in Vivado.
|
|
# Using set_input_delay associates the I/Os to a clock group, but
|
|
# set_(min|max)_delay overwrites the setup/hold analysis values.
|
|
###############################################################################
|
|
|
|
set async_inputs [get_ports {FPGA_AUX_REF}]
|
|
|
|
set_input_delay -clock [get_clocks async_in_clk] 0.000 $async_inputs
|
|
set_max_delay -from $async_inputs 50.000
|
|
set_min_delay -from $async_inputs 0.000
|
|
|
|
|
|
set async_outputs [get_ports {FABRIC_CLK_OUT_P PPS_LED}]
|
|
|
|
set_output_delay -clock [get_clocks async_out_clk] 0.000 $async_outputs
|
|
set_max_delay -to $async_outputs 50.000
|
|
set_min_delay -to $async_outputs 0.000
|