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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
142 lines
4.2 KiB
Plaintext
142 lines
4.2 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.4
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# Date: Fri Mar 8 19:57:57 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx75
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SET devicefamily = spartan6
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
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# END Select
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# BEGIN Parameters
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CSET check_bramcount=false
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CSET component_name=chipscope_ila_32
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CSET constraint_type=external
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CSET counter_width_1=Disabled
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CSET counter_width_10=Disabled
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CSET counter_width_11=Disabled
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CSET counter_width_12=Disabled
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CSET counter_width_13=Disabled
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CSET counter_width_14=Disabled
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CSET counter_width_15=Disabled
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CSET counter_width_16=Disabled
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CSET counter_width_2=Disabled
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CSET counter_width_3=Disabled
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CSET counter_width_4=Disabled
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CSET counter_width_5=Disabled
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CSET counter_width_6=Disabled
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CSET counter_width_7=Disabled
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CSET counter_width_8=Disabled
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CSET counter_width_9=Disabled
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CSET data_port_width=0
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CSET data_same_as_trigger=true
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CSET disable_save_keep=false
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CSET enable_storage_qualification=true
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CSET enable_trigger_output_port=false
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CSET example_design=false
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CSET exclude_from_data_storage_1=false
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CSET exclude_from_data_storage_10=false
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CSET exclude_from_data_storage_11=false
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CSET exclude_from_data_storage_12=false
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CSET exclude_from_data_storage_13=false
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CSET exclude_from_data_storage_14=false
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CSET exclude_from_data_storage_15=false
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CSET exclude_from_data_storage_16=false
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CSET exclude_from_data_storage_2=false
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CSET exclude_from_data_storage_3=false
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CSET exclude_from_data_storage_4=false
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CSET exclude_from_data_storage_5=false
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CSET exclude_from_data_storage_6=false
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CSET exclude_from_data_storage_7=false
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CSET exclude_from_data_storage_8=false
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CSET exclude_from_data_storage_9=false
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CSET match_type_1=basic_with_edges
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CSET match_type_10=basic_with_edges
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CSET match_type_11=basic_with_edges
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CSET match_type_12=basic_with_edges
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CSET match_type_13=basic_with_edges
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CSET match_type_14=basic_with_edges
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CSET match_type_15=basic_with_edges
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CSET match_type_16=basic_with_edges
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CSET match_type_2=basic_with_edges
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CSET match_type_3=basic_with_edges
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CSET match_type_4=basic_with_edges
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CSET match_type_5=basic_with_edges
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CSET match_type_6=basic_with_edges
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CSET match_type_7=basic_with_edges
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CSET match_type_8=basic_with_edges
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CSET match_type_9=basic_with_edges
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CSET match_units_1=1
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CSET match_units_10=1
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CSET match_units_11=1
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CSET match_units_12=1
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CSET match_units_13=1
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CSET match_units_14=1
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CSET match_units_15=1
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CSET match_units_16=1
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CSET match_units_2=1
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CSET match_units_3=1
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CSET match_units_4=1
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CSET match_units_5=1
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CSET match_units_6=1
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CSET match_units_7=1
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CSET match_units_8=1
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CSET match_units_9=1
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CSET max_sequence_levels=1
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CSET number_of_trigger_ports=1
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CSET sample_data_depth=1024
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CSET sample_on=Rising
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CSET trigger_port_width_1=32
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CSET trigger_port_width_10=8
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CSET trigger_port_width_11=8
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CSET trigger_port_width_12=8
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CSET trigger_port_width_13=8
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CSET trigger_port_width_14=8
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CSET trigger_port_width_15=8
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CSET trigger_port_width_16=8
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CSET trigger_port_width_2=8
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CSET trigger_port_width_3=8
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CSET trigger_port_width_4=8
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CSET trigger_port_width_5=8
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CSET trigger_port_width_6=8
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CSET trigger_port_width_7=8
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CSET trigger_port_width_8=8
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CSET trigger_port_width_9=8
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CSET use_rpms=false
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-12-18T02:47:40Z
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# END Extra information
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GENERATE
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# CRC: aad58d16
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