Andrew Moch
05eb1bc2f1
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
436 lines
15 KiB
Systemverilog
436 lines
15 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_chdr_dispatch
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//
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// Description:
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// This module serves as an Ethernet endpoint for CHDR traffic.
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// Ethernet frames arrive on the eth_rx port where they are
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// inspected and classified as CHDR or !CHDR. A frame contains
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// CHDR payload if it is addressed to us (Eth and IP), is a UDP
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// packet and the destination port is one of the CHDR ports.
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// The UDP payload for CHDR frame is sent out of the e2v
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// in addition to source information for Eth, IP and UDP. All
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// other traffic address to us (Eth) is sent to the e2c port.
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// Traffic not addressed (Eth) to us is dropped(optionally).
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//
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// Parameters:
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// - CPU_FIFO_SIZE: log2 size of CPU RX fifo
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// - PREAMBLE_BYTES: Number of bytes in the Preamble
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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// - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
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// - ENET_W: Width of AXI bus going to Ethernet Mac
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//
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// Signals:
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// - eth_rx : The input Ethernet stream from the MAC
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// tUser={error,trailing bytes}
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// - e2v : The output CHDR stream to the rfnoc infrastructure
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// - e2c : The output Ethernet stream to the CPU
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//
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// - my_mac : The Ethernet (MAC) address of this endpoint
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// - my_ip : The IPv4 address of this endpoint
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// - my_udp_chdr_port : The UDP port allocated for CHDR traffic on this endpoint
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//
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module eth_ipv4_chdr_dispatch #(
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int CPU_FIFO_SIZE = $clog2(1558),
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int PREAMBLE_BYTES = 6,
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int MAX_PACKET_BYTES = 2**16-1,
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bit DROP_UNKNOWN_MAC = 0,
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bit DROP_MIN_PACKET = 0,
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int ENET_W = 64
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)(
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// AXI-Stream interfaces
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AxiStreamIf.slave eth_rx, // tUser={error,trailing bytes};
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AxiStreamIf.master e2v, // tUser={1'b0,trailing bytes};
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AxiStreamIf.master e2c, // tUser={1'b0,trailing bytes};
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// Device addresses
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input logic [47:0] my_mac,
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input logic [31:0] my_ip,
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input logic [15:0] my_udp_chdr_port
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);
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localparam ENET_USER_W = $clog2(ENET_W/8)+1;
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//---------------------------------------
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// Include for byte positions
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//---------------------------------------
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`include "eth_constants.vh"
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// example macro to handle interface assignment
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`define AXI4S_ASSIGN(O,I) \
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``O.tdata = ``I.tdata;\
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``O.tuser = ``I.tuser;\
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``O.tlast = ``I.tlast;\
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``O.tvalid = ``I.tvalid;\
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``I.tready = ``O.tready;
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// axi_remov_bytes (PREAMBLE Strip)
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// tUser = {error,trailing bytes};
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AxiStreamPacketIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),
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.TKEEP(0),.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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in0(eth_rx.clk,eth_rx.rst);
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// in_reg
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// tUser = {error,trailing bytes};
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AxiStreamPacketIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),
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.TKEEP(0),.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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in1(eth_rx.clk,eth_rx.rst);
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// STATEMACHINE
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// tUser = {error,trailing bytes};
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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in2(eth_rx.clk,eth_rx.rst);
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// CPU_BRANCH
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// tUser = {error,trailing bytes};
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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cpu0(eth_rx.clk,eth_rx.rst);
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// out_reg_cpu
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// tUser = {error,trailing bytes};
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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cpu1(eth_rx.clk,eth_rx.rst);
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// cpu_out_gate - throw away error packets
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// tUser = {1'b0,trailing bytes};
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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cpu2(eth_rx.clk,eth_rx.rst);
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// cpu_out_fifo
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// e2c (OUTPUT)
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// CHDR_Branch
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// tUser = {error,trailing bytes};
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.TKEEP(0),.TUSER(0))
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chdr0(eth_rx.clk,eth_rx.rst);
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// e2v(OUTPUT)
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//---------------------------------------
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// Strip Bytes
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//---------------------------------------
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if (PREAMBLE_BYTES > 0) begin : gen_strip_preamble
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// Strip the preamble
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axi4s_remove_bytes #(.REM_START(0),.REM_END(PREAMBLE_BYTES-1)
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) strip_preamble (
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.i(eth_rx),.o(in0)
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);
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end else begin : gen_no_preamble
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always_comb begin
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`AXI4S_ASSIGN(in0,eth_rx);
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end
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end
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//---------------------------------------
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// Input pipeline stage
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//---------------------------------------
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axi4s_fifo #(
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.SIZE(1)
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) in_reg_i (
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.clear(1'b0),.space(),.occupied(),
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.i(in0), .o(in1)
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);
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//---------------------------------------
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// Classification state machine
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//---------------------------------------
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typedef enum logic [2:0] {
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ST_IDLE_ETH_L0 = 3'd0,
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ST_FWD_CHDR = 3'd1,
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ST_FWD_CPU = 3'd2,
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ST_DROP_TERM = 3'd3,
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ST_DROP_WAIT = 3'd4
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} dispatch_state_t;
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// State info
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dispatch_state_t dispatch_state,next_dispatch_state = ST_IDLE_ETH_L0;
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logic cpu_error = 1'b0;
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logic chdr_error = 1'b0;
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logic chdr0_error = 1'b0;
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logic mac_error, mac_error_old = 1'b0;
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logic min_packet_error, min_packet_error_old = 1'b0;
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logic reached_min_packet;
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// Cached fields
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logic [47:0] eth_dst_addr_new, eth_src_addr_new;
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logic [31:0] ipv4_dst_addr_new, ipv4_src_addr_new;
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logic [15:0] udp_dst_port_new, udp_src_port_new, eth_type_new;
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logic [7:0] ip_protocol_new, ip_version_new;
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logic [47:0] eth_dst_addr_old, eth_src_addr_old;
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logic [31:0] ipv4_dst_addr_old, ipv4_src_addr_old;
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logic [15:0] udp_dst_port_old, udp_src_port_old, eth_type_old;
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logic [7:0] ip_protocol_old, ip_version_old;
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logic reached_min_packet_new, reached_min_packet_old;
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logic reached_end_of_udp;
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logic eth_dst_is_broadcast;
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logic eth_dst_is_me;
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logic udp_dst_is_me;
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logic ipv4_dst_is_me;
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logic ipv4_protocol_is_udp;
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logic eth_type_is_ipv4;
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// save the fields
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always_ff @(posedge eth_rx.clk) begin : field_ff
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if (eth_rx.rst) begin
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eth_dst_addr_old <= '0;
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eth_src_addr_old <= '0;
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ip_protocol_old <= '0;
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ip_version_old <= '0;
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ipv4_src_addr_old <= '0;
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ipv4_dst_addr_old <= '0;
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udp_src_port_old <= '0;
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udp_dst_port_old <= '0;
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eth_type_old <= '0;
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mac_error_old <= 1'b0;
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min_packet_error_old <= 1'b0;
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reached_min_packet_old <= 1'b0;
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// Statemachine Decisions
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eth_dst_is_broadcast <=1'b0;
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eth_dst_is_me <=1'b0;
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udp_dst_is_me <=1'b0;
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ipv4_dst_is_me <=1'b0;
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ipv4_protocol_is_udp <=1'b0;
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eth_type_is_ipv4 <=1'b0;
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end else begin
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eth_dst_addr_old <= eth_dst_addr_new;
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eth_src_addr_old <= eth_src_addr_new;
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ip_protocol_old <= ip_protocol_new;
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ip_version_old <= ip_version_new;
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ipv4_src_addr_old <= ipv4_src_addr_new;
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ipv4_dst_addr_old <= ipv4_dst_addr_new;
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udp_src_port_old <= udp_src_port_new;
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udp_dst_port_old <= udp_dst_port_new;
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eth_type_old <= eth_type_new;
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if (in0.tvalid && in0.tready) begin
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eth_dst_is_broadcast <= eth_dst_addr_new == ETH_ADDR_BCAST;
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eth_dst_is_me <= eth_dst_addr_new == my_mac;
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udp_dst_is_me <= udp_dst_port_new == my_udp_chdr_port;
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ipv4_dst_is_me <= ipv4_dst_addr_new == my_ip;
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ipv4_protocol_is_udp <= ip_protocol_new == IPV4_PROTO_UDP;
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eth_type_is_ipv4 <= eth_type_new == ETH_TYPE_IPV4;
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end
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if (in1.tvalid && in1.tready) begin
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if (in1.tlast) begin
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mac_error_old <= 1'b0;
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min_packet_error_old <= 1'b0;
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reached_min_packet_old <= 1'b0;
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end else begin
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if (mac_error)
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mac_error_old <= 1'b1;
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if(min_packet_error)
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min_packet_error_old <= 1'b1;
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if(reached_min_packet_new)
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reached_min_packet_old <= 1'b1;
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end
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end
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end
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end
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// get the fields - don't use assign. assign will not activate with changes to in0.
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always_comb begin : get_fields
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eth_dst_addr_new = in0.get_packet_field48(eth_dst_addr_old,DST_MAC_BYTE,.NETWORK_ORDER(1));
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eth_src_addr_new = in0.get_packet_field48(eth_src_addr_old,SRC_MAC_BYTE,.NETWORK_ORDER(1));
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ip_version_new = in0.get_packet_byte(ip_version_old,IP_VERSION_BYTE);
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ip_protocol_new = in0.get_packet_byte(ip_protocol_old,PROTOCOL_BYTE);
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ipv4_src_addr_new = in0.get_packet_field32(ipv4_src_addr_old,SRC_IP_BYTE,.NETWORK_ORDER(1));
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ipv4_dst_addr_new = in0.get_packet_field32(ipv4_dst_addr_old,DST_IP_BYTE,.NETWORK_ORDER(1));
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udp_src_port_new = in0.get_packet_field16(udp_src_port_old,SRC_PORT_BYTE,.NETWORK_ORDER(1));
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udp_dst_port_new = in0.get_packet_field16(udp_dst_port_old,DST_PORT_BYTE,.NETWORK_ORDER(1));
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eth_type_new = in0.get_packet_field16(eth_type_old,ETH_TYPE_BYTE,.NETWORK_ORDER(1));
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end
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always_comb begin : reached_bytes
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reached_min_packet_new = in1.reached_packet_byte(MIN_PACKET_SIZE_BYTE);
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reached_end_of_udp = in1.reached_packet_byte(DST_PORT_BYTE+3);// we have enough to decide
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end
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assign mac_error = in1.tuser[ERROR_BIT] || mac_error_old;
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if (DROP_MIN_PACKET) begin
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assign reached_min_packet = (reached_min_packet_new && in1.tuser[BYTES_MSB:0] ==0) || reached_min_packet_old;
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assign min_packet_error = (in1.tlast && !reached_min_packet) || min_packet_error_old;
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end else begin
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assign reached_min_packet = 1'b1;
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assign min_packet_error = 1'b0;
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end
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always_ff @(posedge eth_rx.clk) begin : dispatch_sm_ff
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if (eth_rx.rst) begin
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dispatch_state <= ST_IDLE_ETH_L0;
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end else begin
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if (in1.tvalid && in1.tready) begin
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if (in1.tlast)
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dispatch_state <= ST_IDLE_ETH_L0;
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else
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dispatch_state <= next_dispatch_state;
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end
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end
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end
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always_comb begin : dispatch_sm_next_state
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//defaults
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next_dispatch_state = dispatch_state;
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`AXI4S_ASSIGN(in2,in1);
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in2.tuser[ERROR_BIT] = mac_error || min_packet_error;
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cpu_error = 1'b0;
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chdr_error = 1'b0;
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// Statemachine always returns to ST_IDLE_ETH_L0 when tlast is set
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case (dispatch_state)
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ST_IDLE_ETH_L0: begin
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cpu_error = 1'b0;
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chdr_error = 1'b0;
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if (mac_error || min_packet_error) begin
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cpu_error = 1'b1;
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chdr_error = 1'b1;
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next_dispatch_state = ST_DROP_TERM;
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end else if (reached_end_of_udp) begin
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// all header values are decoded
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if (eth_dst_is_broadcast) begin
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// If Eth destination is bcast then fwd to CPU
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cpu_error = 1'b0;
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chdr_error = 1'b1;
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next_dispatch_state = ST_FWD_CPU;
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end else if (!eth_dst_is_me && DROP_UNKNOWN_MAC) begin
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// If Eth destination is not us then drop the packet
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cpu_error = 1'b1;
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chdr_error = 1'b1;
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next_dispatch_state = ST_DROP_TERM;
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end else if (udp_dst_is_me &&
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ipv4_dst_is_me &&
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//ip_version_new == IPV4_LEN5 && // NEW CHECK --verify if this is ok
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ipv4_protocol_is_udp &&
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eth_type_is_ipv4) begin
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// The conditions matches CHDR port
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cpu_error = 1'b1;
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chdr_error = 1'b0;
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next_dispatch_state = ST_FWD_CHDR;
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end else begin
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// Not the CHDR port. Forward to CPU
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cpu_error = 1'b0;
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chdr_error = 1'b1;
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next_dispatch_state = ST_FWD_CPU;
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end
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end
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end
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// CHDR Payload
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ST_FWD_CHDR: begin
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cpu_error = 1'b1;
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chdr_error = 1'b0;
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if (mac_error || min_packet_error) begin
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cpu_error = 1'b1;
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chdr_error = 1'b1;
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next_dispatch_state = ST_DROP_TERM;
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end
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end
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// NotCHDR Payload: Send to CPU
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ST_FWD_CPU: begin
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cpu_error = 1'b0;
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chdr_error = 1'b1;
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if (mac_error || min_packet_error) begin
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cpu_error = 1'b1;
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chdr_error = 1'b1;
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next_dispatch_state = ST_DROP_TERM;
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end
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end
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// Unwanted Payload: Drop
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ST_DROP_TERM: begin
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cpu_error = 1'b1;
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chdr_error = 1'b1;
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in2.tlast = 1'b1;
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in2.tvalid = 1'b1;
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in1.tready = in2.tready;
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next_dispatch_state = ST_DROP_WAIT;
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end
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// Unwanted Payload: wait
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ST_DROP_WAIT: begin
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cpu_error = 1'b0;
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chdr_error = 1'b0;
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in2.tlast = 1'b0;
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in2.tvalid = 1'b0;
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in1.tready = 1'b1;
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end
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// We should never get here
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default: begin
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cpu_error = 1'b0;
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chdr_error = 1'b0;
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in1.tready = 1'b1;
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in2.tvalid = 1'b0;
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in2.tlast = 1'b0;
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next_dispatch_state = ST_IDLE_ETH_L0;
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end
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endcase
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end
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//---------------------------------------
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// SPLIT
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//---------------------------------------
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always_comb begin : cpu0_assign
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cpu0.tdata = in2.tdata;
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cpu0.tuser = in2.tuser;
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cpu0.tlast = in2.tlast;
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cpu0.tvalid = in2.tvalid && chdr0.tready;
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cpu0.tuser[ERROR_BIT] = in2.tuser[ERROR_BIT] || cpu_error;
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chdr0.tdata = in2.tdata;
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chdr0.tuser = in2.tuser;
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chdr0.tlast = in2.tlast;
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chdr0.tvalid = in2.tvalid && cpu0.tready;
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chdr0_error = in2.tuser[ERROR_BIT] || chdr_error;
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in2.tready = cpu0.tready && chdr0.tready;
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end
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//---------------------------------------
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// CPU Output processing
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//---------------------------------------
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axi4s_fifo #(
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.SIZE(1)
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) out_reg_cpu_i (
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.clear(),.space(),.occupied(),
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.i(cpu0),.o(cpu1)
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);
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// We cannot make a CHDR/noCHDR routing decision until we are in the middle
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// of a packet so we use a packet gate for the CPU path because we can rewind
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// the write pointer and drop the packet in case it's destined for the CHDR
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// path.
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// NOTE: This also rejects packets with FCS failures.
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// NOTE: The SIZE of this FIFO must accommodate a 9000 byte jumbo frame
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// regardless of the CHDR MTU
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// SIZED for 11 bit address when using a 64 bit word -> 16KByte
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// SIZED for 8 bit address when using a 512 bit word -> 16KByte
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axi4s_packet_gate #(
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.SIZE(17-$clog2(ENET_W)), .USE_AS_BUFF(0)
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) cpu_out_gate_i (
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.clear(1'b0), .error(cpu1.tuser[ERROR_BIT]),
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.i(cpu1),.o(cpu2)
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);
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// The CPU can be slow to respond (relative to packet wirespeed) so
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// extra buffer for packets destined there so it doesn't back up.
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|
axi4s_fifo #(
|
|
.SIZE(CPU_FIFO_SIZE)
|
|
) cpu_fifo_i (
|
|
.clear(),.space(),.occupied(),
|
|
.i(cpu2),.o(e2c)
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|
);
|
|
|
|
// CHDR DATA GATE
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|
// SIZED for 11 bit address when using a 64 bit word -> 16KByte
|
|
// SIZED for 8 bit address when using a 512 bit word -> 16KByte
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axi4s_packet_gate #(
|
|
.SIZE(17-$clog2(ENET_W))
|
|
) chdr_out_gate_i (
|
|
.clear(1'b0),.error(chdr0_error),
|
|
.i(chdr0),.o(e2v)
|
|
);
|
|
|
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endmodule // eth_ipv4_chdr_dispatch
|