Martin Braun
e44fe8625b
The module was failing with missing wire types when instantiated from another module with a default wiretype of 'none'. To fix this, this module was also moved to no default wire type. Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
52 lines
1.1 KiB
Verilog
52 lines
1.1 KiB
Verilog
//
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// Copyright 2014 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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`default_nettype none
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module synchronizer_impl #(
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parameter WIDTH = 1,
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parameter STAGES = 2,
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parameter INITIAL_VAL = 0
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)(
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input wire clk,
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input wire rst,
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input wire [WIDTH-1:0] in,
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output wire [WIDTH-1:0] out
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);
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(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] value[0:STAGES-1];
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integer k;
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initial begin
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for (k = 0; k < STAGES; k = k + 1) begin
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value[k] = INITIAL_VAL;
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end
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end
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genvar i;
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generate
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for (i=0; i<STAGES; i=i+1) begin: stages
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always @(posedge clk) begin
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if (rst) begin
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value[i] <= INITIAL_VAL;
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end else begin
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if (i == 0) begin
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value[i] <= in;
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end else begin
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value[i] <= value[i-1];
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end
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end
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end
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end
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endgenerate
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assign out = value[STAGES-1];
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endmodule //synchronizer_impl
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`default_nettype wire
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