65 lines
1.5 KiB
Plaintext
65 lines
1.5 KiB
Plaintext
The following files were generated for 'hbdec2' in directory
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/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
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Opens the IP Customization GUI:
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Allows the user to customize or recustomize the IP instance.
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* hbdec2.mif
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* hbdec2_reload_order.txt
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XCO file generator:
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Generate an XCO file for compatibility with legacy flows.
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* hbdec2.xco
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Creates an implementation netlist:
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Creates an implementation netlist for the IP.
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* hbdec2.ngc
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* hbdec2.v
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* hbdec2.veo
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* hbdec2COEFF_auto0_0.mif
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* hbdec2COEFF_auto0_1.mif
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* hbdec2COEFF_auto0_2.mif
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* hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
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* hbdec2_reload_addrfilt_decode_rom.mif
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* hbdec2filt_decode_rom.mif
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Creates an HDL instantiation template:
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Creates an HDL instantiation template for the IP.
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* hbdec2.veo
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IP Symbol Generator:
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Generate an IP symbol based on the current project options'.
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* hbdec2.asy
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* hbdec2.mif
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* hbdec2_reload_order.txt
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Generate ISE metadata:
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Create a metadata file for use when including this core in ISE designs
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* hbdec2_xmdf.tcl
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Generate ISE subproject:
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Create an ISE subproject for use when including this core in ISE designs
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* hbdec2.gise
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* hbdec2.xise
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Deliver Readme:
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Readme file for the IP.
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* hbdec2_readme.txt
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Generate FLIST file:
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Text file listing all of the output files produced when a customized core was
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generated in the CORE Generator.
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* hbdec2_flist.txt
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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