98 lines
1.6 KiB
Verilog
98 lines
1.6 KiB
Verilog
`timescale 1ns/1ps
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module catgen_tb();
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wire GSR, GTS;
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glbl glbl( );
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reg clk = 0;
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reg reset = 1;
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wire ddrclk;
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always #100 clk = ~clk;
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initial $dumpfile("catgen_tb.vcd");
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initial $dumpvars(0,catgen_tb);
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wire [11:0] pins;
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wire frame;
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reg mimo;
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reg [7:0] count;
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reg tx_strobe;
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wire [11:0] i0 = {4'hA,count};
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wire [11:0] q0 = {4'hB,count};
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wire [11:0] i1 = {4'hC,count};
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wire [11:0] q1 = {4'hD,count};
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initial
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begin
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#1000 reset = 0;
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BURST(4);
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BURST(5);
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MIMO_BURST(4);
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MIMO_BURST(5);
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#2000;
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$finish;
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end
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task BURST;
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input [7:0] len;
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begin
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tx_strobe <= 0;
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mimo <= 0;
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count <= 0;
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@(posedge clk);
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@(posedge clk);
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repeat(len)
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begin
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tx_strobe <= 1;
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@(posedge clk);
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count <= count + 1;
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end
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tx_strobe <= 0;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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end
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endtask // BURST
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task MIMO_BURST;
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input [7:0] len;
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begin
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tx_strobe <= 0;
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mimo <= 1;
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count <= 0;
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@(posedge clk);
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@(posedge clk);
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repeat(len)
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begin
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tx_strobe <= 1;
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@(posedge clk);
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tx_strobe <= 0;
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@(posedge clk);
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count <= count + 1;
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end
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tx_strobe <= 0;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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end
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endtask // BURST
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catgen_ddr_cmos catgen
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(.data_clk(ddrclk),
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.reset(reset),
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.mimo(mimo),
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.tx_frame(frame),
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.tx_d(pins),
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.tx_clk(clk),
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.tx_strobe(tx_strobe),
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.i0(i0),.q0(q0),
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.i1(i1),.q1(q1));
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endmodule // hb_chain_tb
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