50 lines
1.3 KiB
Verilog
50 lines
1.3 KiB
Verilog
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module catgen_ddr_cmos
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(output data_clk,
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input reset,
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input mimo,
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output tx_frame,
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output [11:0] tx_d,
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input tx_clk, output reg tx_strobe,
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input [11:0] i0, input [11:0] q0,
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input [11:0] i1, input [11:0] q1);
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//IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
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//clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
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reg [11:0] i,q;
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genvar z;
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reg tx_strobe_d;
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generate
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for(z = 0; z < 12; z = z + 1)
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begin : gen_pins
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ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2
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(.Q(tx_d[z]), .C0(tx_clk), .C1(~tx_clk),
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.CE(1'b1), .D0(i[z]), .D1(q[z]), .R(1'b0), .S(1'b0));
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end
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endgenerate
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ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_frame
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(.Q(tx_frame), .C0(tx_clk), .C1(~tx_clk),
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.CE(1'b1), .D0(tx_strobe_d), .D1(mimo&tx_strobe_d), .R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_clk
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(.Q(data_clk), .C0(tx_clk), .C1(~tx_clk),
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.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
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always @(posedge tx_clk)
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tx_strobe <= (mimo)? ~tx_strobe : 1'b1;
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always @(posedge tx_clk)
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tx_strobe_d <= tx_strobe;
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always @(posedge tx_clk)
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if(tx_strobe)
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{i,q} <= {i0,q0};
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else
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{i,q} <= {i1,q1};
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endmodule // catgen_ddr_cmos
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