40 lines
886 B
Verilog
40 lines
886 B
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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//
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// Use this module in conjunction with settings_bus.v to add stateful reads
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// to the settings bis. This enables you to do things like have registers reset atomicly
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// as they are read. It also pipelines the address path to ease timing.
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//
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module settings_readback
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#(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
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(
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input wb_clk,
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input wb_rst,
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input [AWIDTH-1:0] wb_adr_i,
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input wb_stb_i,
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input wb_we_i,
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input [DWIDTH-1:0] rb_data,
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output reg [RB_ADDRW-1:0] rb_addr,
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output [DWIDTH-1:0] wb_dat_o,
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output reg rb_rd_stb
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);
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always @(posedge wb_clk)
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if (wb_stb_i && ~wb_we_i) begin
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rb_addr <= wb_adr_i[RB_ADDRW+1:2];
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rb_rd_stb <= 1'b1;
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end else begin
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rb_rd_stb <= 1'b0;
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end
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assign wb_dat_o = rb_data;
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endmodule // settings_readback
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