56 lines
1.1 KiB
Verilog
56 lines
1.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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`timescale 1ns / 1ps
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module time_transfer_tb();
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reg clk = 0, rst = 1;
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always #5 clk = ~clk;
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initial
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begin
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@(negedge clk);
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@(negedge clk);
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rst <= 0;
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end
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initial $dumpfile("time_transfer_tb.vcd");
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initial $dumpvars(0,time_transfer_tb);
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initial #100000000 $finish;
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wire exp_time, pps, pps_rcv;
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wire [63:0] vita_time_rcv;
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reg [63:0] vita_time = 0;
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reg [63:0] counter = 0;
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localparam PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
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always @(posedge clk)
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if(counter == PPS_PERIOD)
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counter <= 0;
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else
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counter <= counter + 1;
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assign pps = (counter == (PPS_PERIOD-1));
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always @(posedge clk)
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vita_time <= vita_time + 1;
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time_sender time_sender
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(.clk(clk),.rst(rst),
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.vita_time(vita_time),
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.send_sync(pps),
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.exp_time_out(exp_time) );
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time_receiver time_receiver
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(.clk(clk),.rst(rst),
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.vita_time(vita_time_rcv),
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.sync_rcvd(pps_rcv),
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.exp_time_in(exp_time) );
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wire [31:0] delta = vita_time - vita_time_rcv;
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endmodule // time_transfer_tb
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