23 lines
481 B
Verilog
23 lines
481 B
Verilog
//
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// Copyright 2014 Ettus Research LLC
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//
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module pps_generator
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#(parameter CLK_FREQ=0, DUTY=25)
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(input clk, input reset, output pps);
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reg[31:0] count;
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always @(posedge clk) begin
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if (reset) begin
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count <= 32'b1;
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end else if (count >= CLK_FREQ) begin
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count <= 32'b1;
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end else begin
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count <= count + 1'b1;
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end
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end
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assign pps = (count < CLK_FREQ * DUTY / 100);
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endmodule //pps_generator
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