27 lines
452 B
Verilog
27 lines
452 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module delay_line
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#(parameter WIDTH=32)
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(input clk,
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input [3:0] delay,
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input [WIDTH-1:0] din,
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output [WIDTH-1:0] dout);
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genvar i;
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generate
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for (i=0;i<WIDTH;i=i+1)
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begin : gen_delay
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SRL16E
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srl16e(.Q(dout[i]),
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.A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
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.CE(1),.CLK(clk),.D(din[i]));
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end
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endgenerate
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endmodule // delay_line
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